Weiming Zhao 12e13fe224 Fix PR20056: Implement pseudo LDR <reg>, =<literal/label> for AArch64 ... This patch is based on the changes from ARM target [1,2] Based on ARM doc [3], if the literal value can be loaded with a valid MOV, it can emit that instruction. This is implemented in this patch. [1] Fix PR18345: ldr= pseudo instruction produces incorrect code when using in inline assembly Author: David Peixotto <dpeixott@codeaurora.org> commit b92cca222898d87bbc764fa22e805adb04ef7f13 (r200777) [2] Implement the ldr-pseudo opcode for ARM assembly Author: David Peixotto <dpeixott@codeaurora.org> commit 0fa193b08627927ccaa0804a34d80480894614b8 (r197708) [3] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802a/CJAHAIBC.html Differential Revision: http://reviews.llvm.org/D4163 llvm-svn: 211533		2014-06-23 20:44:16 +00:00
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llvm	Fix PR20056: Implement pseudo LDR <reg>, =<literal/label> for AArch64	2014-06-23 20:44:16 +00:00
llvm-c	Remove support for LLVM runtime multi-threading.	2014-06-19 18:18:23 +00:00