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303 lines
8.9 KiB
Plaintext
303 lines
8.9 KiB
Plaintext
Target Independent Opportunities:
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//===---------------------------------------------------------------------===//
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We should make the following changes to clean up MachineInstr:
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1. Add an Opcode field to TargetInstrDescriptor, so you can tell the opcode of
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an instruction with just a TargetInstrDescriptor*.
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2. Remove the Opcode field from MachineInstr, replacing it with a
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TargetInstrDescriptor*.
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3. Getting information about a machine instr then becomes:
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MI->getInfo()->isTwoAddress()
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instead of:
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const TargetInstrInfo &TII = ...
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TII.isTwoAddrInstr(MI->getOpcode())
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//===---------------------------------------------------------------------===//
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FreeBench/mason contains code like this:
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static p_type m0u(p_type p) {
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int m[]={0, 8, 1, 2, 16, 5, 13, 7, 14, 9, 3, 4, 11, 12, 15, 10, 17, 6};
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p_type pu;
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pu.a = m[p.a];
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pu.b = m[p.b];
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pu.c = m[p.c];
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return pu;
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}
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We currently compile this into a memcpy from a static array into 'm', then
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a bunch of loads from m. It would be better to avoid the memcpy and just do
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loads from the static array.
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//===---------------------------------------------------------------------===//
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Make the PPC branch selector target independant
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//===---------------------------------------------------------------------===//
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Get the C front-end to expand hypot(x,y) -> llvm.sqrt(x*x+y*y) when errno and
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precision don't matter (ffastmath). Misc/mandel will like this. :)
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//===---------------------------------------------------------------------===//
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Solve this DAG isel folding deficiency:
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int X, Y;
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void fn1(void)
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{
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X = X | (Y << 3);
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}
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compiles to
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fn1:
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movl Y, %eax
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shll $3, %eax
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orl X, %eax
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movl %eax, X
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ret
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The problem is the store's chain operand is not the load X but rather
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a TokenFactor of the load X and load Y, which prevents the folding.
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There are two ways to fix this:
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1. The dag combiner can start using alias analysis to realize that y/x
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don't alias, making the store to X not dependent on the load from Y.
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2. The generated isel could be made smarter in the case it can't
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disambiguate the pointers.
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Number 1 is the preferred solution.
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This has been "fixed" by a TableGen hack. But that is a short term workaround
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which will be removed once the proper fix is made.
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//===---------------------------------------------------------------------===//
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On targets with expensive 64-bit multiply, we could LSR this:
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for (i = ...; ++i) {
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x = 1ULL << i;
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into:
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long long tmp = 1;
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for (i = ...; ++i, tmp+=tmp)
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x = tmp;
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This would be a win on ppc32, but not x86 or ppc64.
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//===---------------------------------------------------------------------===//
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Shrink: (setlt (loadi32 P), 0) -> (setlt (loadi8 Phi), 0)
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//===---------------------------------------------------------------------===//
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Reassociate should turn: X*X*X*X -> t=(X*X) (t*t) to eliminate a multiply.
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//===---------------------------------------------------------------------===//
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Interesting? testcase for add/shift/mul reassoc:
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int bar(int x, int y) {
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return x*x*x+y+x*x*x*x*x*y*y*y*y;
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}
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int foo(int z, int n) {
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return bar(z, n) + bar(2*z, 2*n);
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}
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//===---------------------------------------------------------------------===//
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These two functions should generate the same code on big-endian systems:
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int g(int *j,int *l) { return memcmp(j,l,4); }
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int h(int *j, int *l) { return *j - *l; }
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this could be done in SelectionDAGISel.cpp, along with other special cases,
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for 1,2,4,8 bytes.
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//===---------------------------------------------------------------------===//
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This code:
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int rot(unsigned char b) { int a = ((b>>1) ^ (b<<7)) & 0xff; return a; }
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Can be improved in two ways:
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1. The instcombiner should eliminate the type conversions.
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2. The X86 backend should turn this into a rotate by one bit.
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//===---------------------------------------------------------------------===//
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Add LSR exit value substitution. It'll probably be a win for Ackermann, etc.
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//===---------------------------------------------------------------------===//
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It would be nice to revert this patch:
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http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20060213/031986.html
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And teach the dag combiner enough to simplify the code expanded before
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legalize. It seems plausible that this knowledge would let it simplify other
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stuff too.
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//===---------------------------------------------------------------------===//
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For packed types, TargetData.cpp::getTypeInfo() returns alignment that is equal
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to the type size. It works but can be overly conservative as the alignment of
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specific packed types are target dependent.
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//===---------------------------------------------------------------------===//
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We should add 'unaligned load/store' nodes, and produce them from code like
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this:
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v4sf example(float *P) {
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return (v4sf){P[0], P[1], P[2], P[3] };
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}
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//===---------------------------------------------------------------------===//
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We should constant fold packed type casts at the LLVM level, regardless of the
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cast. Currently we cannot fold some casts because we don't have TargetData
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information in the constant folder, so we don't know the endianness of the
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target!
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//===---------------------------------------------------------------------===//
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Add support for conditional increments, and other related patterns. Instead
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of:
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movl 136(%esp), %eax
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cmpl $0, %eax
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je LBB16_2 #cond_next
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LBB16_1: #cond_true
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incl _foo
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LBB16_2: #cond_next
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emit:
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movl _foo, %eax
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cmpl $1, %edi
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sbbl $-1, %eax
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movl %eax, _foo
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//===---------------------------------------------------------------------===//
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Combine: a = sin(x), b = cos(x) into a,b = sincos(x).
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Expand these to calls of sin/cos and stores:
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double sincos(double x, double *sin, double *cos);
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float sincosf(float x, float *sin, float *cos);
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long double sincosl(long double x, long double *sin, long double *cos);
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Doing so could allow SROA of the destination pointers. See also:
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=17687
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//===---------------------------------------------------------------------===//
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Scalar Repl cannot currently promote this testcase to 'ret long cst':
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%struct.X = type { int, int }
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%struct.Y = type { %struct.X }
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ulong %bar() {
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%retval = alloca %struct.Y, align 8 ; <%struct.Y*> [#uses=3]
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%tmp12 = getelementptr %struct.Y* %retval, int 0, uint 0, uint 0
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store int 0, int* %tmp12
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%tmp15 = getelementptr %struct.Y* %retval, int 0, uint 0, uint 1
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store int 1, int* %tmp15
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%retval = cast %struct.Y* %retval to ulong*
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%retval = load ulong* %retval ; <ulong> [#uses=1]
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ret ulong %retval
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}
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it should be extended to do so.
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//===---------------------------------------------------------------------===//
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Turn this into a single byte store with no load (the other 3 bytes are
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unmodified):
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void %test(uint* %P) {
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%tmp = load uint* %P
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%tmp14 = or uint %tmp, 3305111552
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%tmp15 = and uint %tmp14, 3321888767
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store uint %tmp15, uint* %P
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ret void
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}
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//===---------------------------------------------------------------------===//
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dag/inst combine "clz(x)>>5 -> x==0" for 32-bit x.
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Compile:
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int bar(int x)
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{
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int t = __builtin_clz(x);
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return -(t>>5);
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}
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to:
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_bar: addic r3,r3,-1
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subfe r3,r3,r3
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blr
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//===---------------------------------------------------------------------===//
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Legalize should lower ctlz like this:
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ctlz(x) = popcnt((x-1) & ~x)
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on targets that have popcnt but not ctlz. itanium, what else?
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//===---------------------------------------------------------------------===//
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quantum_sigma_x in 462.libquantum contains the following loop:
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for(i=0; i<reg->size; i++)
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{
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/* Flip the target bit of each basis state */
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reg->node[i].state ^= ((MAX_UNSIGNED) 1 << target);
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}
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Where MAX_UNSIGNED/state is a 64-bit int. On a 32-bit platform it would be just
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so cool to turn it into something like:
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long long Res = ((MAX_UNSIGNED) 1 << target);
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if (target < 32) {
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for(i=0; i<reg->size; i++)
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reg->node[i].state ^= Res & 0xFFFFFFFFULL;
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} else {
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for(i=0; i<reg->size; i++)
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reg->node[i].state ^= Res & 0xFFFFFFFF00000000ULL
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}
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... which would only do one 32-bit XOR per loop iteration instead of two.
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It would also be nice to recognize the reg->size doesn't alias reg->node[i], but
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alas...
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//===---------------------------------------------------------------------===//
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This isn't recognized as bswap by instcombine:
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unsigned int swap_32(unsigned int v) {
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v = ((v & 0x00ff00ffU) << 8) | ((v & 0xff00ff00U) >> 8);
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v = ((v & 0x0000ffffU) << 16) | ((v & 0xffff0000U) >> 16);
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return v;
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}
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//===---------------------------------------------------------------------===//
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These should turn into single 16-bit (unaligned?) loads on little/big endian
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processors.
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unsigned short read_16_le(const unsigned char *adr) {
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return adr[0] | (adr[1] << 8);
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}
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unsigned short read_16_be(const unsigned char *adr) {
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return (adr[0] << 8) | adr[1];
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}
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//===---------------------------------------------------------------------===//
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