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1a0155bc19
The isReMaterlizable flag is somewhat confusing, unlike most other instruction flags it is currently interpreted as a hint (mightBeRematerializable would be a better name). While LUI is always rematerialisable, for an instruction like ADDI it depends on its operands. TargetInstrInfo::isTriviallyReMaterializable will call TargetInstrInfo::isReallyTriviallyReMaterializable, which in turn calls TargetInstrInfo::isReallyTriviallyReMaterializableGeneric. We rely on the logic in the latter to pick out instances of ADDI that really are rematerializable. The isReMaterializable flag does make a difference on a variety of test programs. The recently committed remat.ll test case demonstrates how stack usage is reduce and a unnecessary lw/sw can be removed. Stack usage in the Proc0 function in dhrystone reduces from 192 bytes to 112 bytes. For the sake of completeness, this patch also implements RISCVRegisterInfo::isConstantPhysReg. Although this is called from a number of places, it doesn't seem to result in different codegen for any programs I've thrown at it. However, it is called in the rematerialisation codepath and it seems sensible to implement something correct here. Differential Revision: https://reviews.llvm.org/D46182 llvm-svn: 332617
115 lines
3.9 KiB
C++
115 lines
3.9 KiB
C++
//===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the RISCV implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVRegisterInfo.h"
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#include "RISCV.h"
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#include "RISCVSubtarget.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#define GET_REGINFO_TARGET_DESC
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#include "RISCVGenRegisterInfo.inc"
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using namespace llvm;
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RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
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: RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
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/*PC*/0, HwMode) {}
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const MCPhysReg *
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RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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return CSR_SaveList;
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}
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BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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// Use markSuperRegs to ensure any register aliases are also reserved
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markSuperRegs(Reserved, RISCV::X0); // zero
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markSuperRegs(Reserved, RISCV::X1); // ra
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markSuperRegs(Reserved, RISCV::X2); // sp
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markSuperRegs(Reserved, RISCV::X3); // gp
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markSuperRegs(Reserved, RISCV::X4); // tp
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markSuperRegs(Reserved, RISCV::X8); // fp
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assert(checkAllSuperRegsMarked(Reserved));
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return Reserved;
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}
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bool RISCVRegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
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return PhysReg == RISCV::X0;
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}
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const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
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return CSR_NoRegs_RegMask;
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}
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void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
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MachineInstr &MI = *II;
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MachineFunction &MF = *MI.getParent()->getParent();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
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DebugLoc DL = MI.getDebugLoc();
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int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
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unsigned FrameReg;
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int Offset =
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getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) +
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MI.getOperand(FIOperandNum + 1).getImm();
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if (!isInt<32>(Offset)) {
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report_fatal_error(
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"Frame offsets outside of the signed 32-bit range not supported");
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}
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MachineBasicBlock &MBB = *MI.getParent();
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bool FrameRegIsKill = false;
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if (!isInt<12>(Offset)) {
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assert(isInt<32>(Offset) && "Int32 expected");
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// The offset won't fit in an immediate, so use a scratch register instead
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// Modify Offset and FrameReg appropriately
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unsigned ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
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TII->movImm32(MBB, II, DL, ScratchReg, Offset);
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BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
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.addReg(FrameReg)
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.addReg(ScratchReg, RegState::Kill);
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Offset = 0;
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FrameReg = ScratchReg;
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FrameRegIsKill = true;
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}
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MI.getOperand(FIOperandNum)
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.ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
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}
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unsigned RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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const TargetFrameLowering *TFI = getFrameLowering(MF);
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return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
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}
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const uint32_t *
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RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & /*MF*/,
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CallingConv::ID /*CC*/) const {
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return CSR_RegMask;
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}
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