RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 19:23:23 +01:00
Code Issues Projects Releases Wiki Activity
9577acaf56
llvm-mirror/test/CodeGen/Thumb2/LowOverheadLoops
History
David Green 169d672b6b [ARM] Improve handling of empty VPT blocks in tail predicated loops 
A vpt block that just contains either VPST;VCTP or VPT;VCTP, once the
VCTP is removed will become invalid. This fixed the first by removing
the now empty block and bails out for the second, as we have no simple
way of converting a VPT to a VCMP.

Differential Revision: https://reviews.llvm.org/D92369
2020-12-14 11:17:01 +00:00
..
add_reduce.mir [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
begin-vpt-without-inst.mir [ARM] Change VPT state assertion 2020-09-30 08:01:10 +01:00
biquad-cascade-default.mir [ARM] Revert low overhead loops with calls before registry allocation. 2020-12-07 15:44:40 +00:00
biquad-cascade-optsize-strd-lr.mir [ARM] Revert low overhead loops with calls before registry allocation. 2020-12-07 15:44:40 +00:00
biquad-cascade-optsize.mir [NFC][ARM] Add more LowOverheadLoop tests. 2020-09-30 12:20:07 +01:00
branch-targets.ll [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
clear-maskedinsts.ll [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
cmplx_cong.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
cond-mov.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
cond-vector-reduce-mve-codegen.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
count_dominates_start.mir [ARM][RegAlloc] Add t2LoopEndDec 2020-12-10 12:14:23 +00:00
ctlz-non-zeros.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
disjoint-vcmp.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
dont-ignore-vctp.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
dont-remove-loop-update.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
emptyblock.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
end-positive-offset.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
exitcount.ll [ARM] Make t2DoLoopStartTP a terminator 2020-12-11 09:23:57 +00:00
extending-loads.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
extract-element.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
fast-fp-loops.ll [ARM][RegAlloc] Add t2LoopEndDec 2020-12-10 12:14:23 +00:00
incorrect-sub-8.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
incorrect-sub-16.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
incorrect-sub-32.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
inlineasm.ll [ARM] Deliberately prevent inline asm in low overhead loops. NFC 2020-11-19 13:28:21 +00:00
inloop-vpnot-1.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
inloop-vpnot-2.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
inloop-vpnot-3.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
inloop-vpsel-1.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
inloop-vpsel-2.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
invariant-qreg.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
it-block-chain-store.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
it-block-chain.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
it-block-itercount.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
it-block-mov.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
it-block-random.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
iv-two-vcmp-reordered.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
iv-two-vcmp.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
iv-vcmp.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
livereg-no-loop-def.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
loop-dec-copy-chain.mir [ARM] Revert low overhead loops with calls before registry allocation. 2020-12-07 15:44:40 +00:00
loop-dec-copy-prev-iteration.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
loop-dec-liveout.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
loop-guards.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
lsr-profitable-chain.ll
lstp-insertion-position.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
massive.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
matrix-debug.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
matrix.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
memcall.ll [ARM] Treat memcpy/memset/memmove as call instructions for low overhead loops 2020-11-03 11:53:09 +00:00
minloop.ll [ARM][RegAlloc] Add t2LoopEndDec 2020-12-10 12:14:23 +00:00
mov-after-dls.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
mov-after-dlstp.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
mov-lr-terminator.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
mov-operand.ll [ARM] Make t2DoLoopStartTP a terminator 2020-12-11 09:23:57 +00:00
move-def-before-start.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
move-start-after-def.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
multi-block-cond-iter-count.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
multi-cond-iter-count.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
multiblock-massive.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
multiple-do-loops.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
mve-float-loops.ll [ARM][RegAlloc] Add t2LoopEndDec 2020-12-10 12:14:23 +00:00
mve-tail-data-types.ll [ARM] Disable WLSTP loops 2020-11-20 13:30:44 +00:00
nested.ll [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
no-dec-cbnz.mir [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
no-dec-le-simple.ll
no-dec-reorder.mir [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
no-dec.mir [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
no-vpsel-liveout.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
non-masked-load.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
non-masked-store.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
out-of-range-cbz.mir
predicated-invariant.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
predicated-liveout-unknown-lanes.ll [Thumb2] Regenerate predicated-liveout-unknown-lanes.ll test 2020-12-02 18:00:42 +00:00
predicated-liveout.mir [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
reductions-vpt-liveout.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
reductions.ll [ARM] Make t2DoLoopStartTP a terminator 2020-12-11 09:23:57 +00:00
remat-vctp.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
remove-elem-moves.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
revert-after-call.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
revert-after-read.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
revert-after-write.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
revert-non-header.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
revert-non-loop.mir [ARM] Revert low overhead loops with calls before registry allocation. 2020-12-07 15:44:40 +00:00
revert-while.mir
revertcallearly.mir [ARM] Revert low overhead loops with calls before registry allocation. 2020-12-07 15:44:40 +00:00
safe-def-no-mov.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
safe-retaining.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
sibling-loops.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
size-limit.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
skip-debug.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
switch.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
tail-pred-basic.ll [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
tail-pred-const.ll [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
tail-pred-disabled-in-loloops.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
tail-pred-intrinsic-add-sat.ll [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
tail-pred-intrinsic-fabs.ll [ARM] Make MachineVerifier more strict about terminators 2020-08-27 07:10:20 +01:00
tail-pred-intrinsic-round.ll [ARM] Cleanup for the MVETailPrediction pass 2020-11-26 15:10:44 +00:00
tail-pred-intrinsic-sub-sat.ll [ARM] Fixup of a few test cases. NFC. 2020-09-09 11:14:44 +01:00
tail-pred-narrow.ll [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
tail-pred-pattern-fail.ll [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
tail-pred-reduce.ll [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
tail-pred-widen.ll [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
tp-multiple-vpst.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
unpredicated-max.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
unpredload.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
unrolled-and-vector.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
unsafe-cpsr-loop-def.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
unsafe-cpsr-loop-use.mir [ARM] Revert low overhead loops with calls before registry allocation. 2020-12-07 15:44:40 +00:00
unsafe-retaining.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
unsafe-use-after.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
vaddv.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
varying-outer-2d-reduction.ll [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
vcmp-vpst-combination-across-blocks.mir [ARM][LowOverheadLoops] Convert intermediate vpr use assertion to condition 2020-11-19 17:15:45 +00:00
vcmp-vpst-combination.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
vctp16-reduce.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
vctp-add-operand-liveout.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
vctp-in-vpt-2.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
vctp-in-vpt.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
vctp-subi3.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
vctp-subri12.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
vctp-subri.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
vector-arith-codegen.ll [ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LR 2020-11-10 16:28:57 +00:00
vector-reduce-mve-tail.ll [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
vector-unroll.ll [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
vmaxmin_vpred_r.mir
vmldava_in_vpt.mir
vpt-blocks.mir [ARM] Improve handling of empty VPT blocks in tail predicated loops 2020-12-14 11:17:01 +00:00
while-loops.ll [ARM] Make t2DoLoopStartTP a terminator 2020-12-11 09:23:57 +00:00
while-negative-offset.mir
while.mir
wlstp.mir [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
wrong-liveout-lsr-shift.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
wrong-vctp-opcode-liveout.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00
wrong-vctp-operand-liveout.mir [ARM] Alter t2DoLoopStart to define lr 2020-11-10 15:57:58 +00:00