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llvm-mirror/test/CodeGen/X86/live-out-reg-info.ll
Sanjay Patel d30aaf33b0 [x86] swap order of srl (and X, C1), C2 when it saves size
The (non-)obvious win comes from saving 3 bytes by using the 0x83 'and' opcode variant instead of 0x81. 
There are also better improvements based on known-bits that allow us to eliminate the mask entirely.

As noted, this could be extended. There are potentially other wins from always shifting first, but doing
that reveals a tangle of problems in other pattern matching. We do this transform generically in 
instcombine, but we often have icmp IR that doesn't match that pattern, so we must account for this
in the backend.

Differential Revision: https://reviews.llvm.org/D38181

llvm-svn: 314023
2017-09-22 19:37:21 +00:00

36 lines
868 B
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
; Make sure dagcombine doesn't eliminate the comparison due
; to an off-by-one bug with computeKnownBits information.
declare void @qux()
define void @foo(i32 %a) {
; CHECK-LABEL: foo:
; CHECK: # BB#0:
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .Lcfi0:
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: shrl $23, %edi
; CHECK-NEXT: btl $8, %edi
; CHECK-NEXT: jb .LBB0_2
; CHECK-NEXT: # BB#1: # %true
; CHECK-NEXT: callq qux
; CHECK-NEXT: .LBB0_2: # %false
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
%t0 = lshr i32 %a, 23
br label %next
next:
%t1 = and i32 %t0, 256
%t2 = icmp eq i32 %t1, 0
br i1 %t2, label %true, label %false
true:
call void @qux()
ret void
false:
ret void
}