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1cf3918f57
This teach simplifyDemandedBits to handle constant splat vector shifts. This required changing some uses of getZExtValue to getLimitedValue since we can't rely on legalization using getShiftAmountTy for the shift amount. I believe there may have been a bug in the ((X << C1) >>u ShAmt) handling where we didn't check if the inner shift was too large. I've fixed that here. I had to add new patterns to ARM because the zext/sext the patterns were trying to look for got turned into an any_extend with this patch. Happy to split that out too, but not sure how to test without this change. Differential Revision: https://reviews.llvm.org/D37665 llvm-svn: 314139
130 lines
4.7 KiB
LLVM
130 lines
4.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=NARROW
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.2 -x86-experimental-vector-widening-legalization | FileCheck %s --check-prefix=WIDE
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; FIXME: We shouldn't require both a movd and an insert in the wide version.
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define void @update(i64* %dst_i, i64* %src_i, i32 %n) nounwind {
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; NARROW-LABEL: update:
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; NARROW: # BB#0: # %entry
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; NARROW-NEXT: subl $12, %esp
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; NARROW-NEXT: movl $0, (%esp)
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; NARROW-NEXT: pcmpeqd %xmm0, %xmm0
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; NARROW-NEXT: movdqa {{.*#+}} xmm1 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
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; NARROW-NEXT: jmp .LBB0_1
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; NARROW-NEXT: .p2align 4, 0x90
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; NARROW-NEXT: .LBB0_2: # %forbody
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; NARROW-NEXT: # in Loop: Header=BB0_1 Depth=1
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; NARROW-NEXT: movl (%esp), %eax
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; NARROW-NEXT: leal (,%eax,8), %ecx
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; NARROW-NEXT: movl {{[0-9]+}}(%esp), %edx
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; NARROW-NEXT: addl %ecx, %edx
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; NARROW-NEXT: movl %edx, {{[0-9]+}}(%esp)
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; NARROW-NEXT: addl {{[0-9]+}}(%esp), %ecx
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; NARROW-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; NARROW-NEXT: pmovzxbw {{.*#+}} xmm2 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
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; NARROW-NEXT: psubw %xmm0, %xmm2
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; NARROW-NEXT: psllw $8, %xmm2
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; NARROW-NEXT: psraw $8, %xmm2
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; NARROW-NEXT: psrlw $2, %xmm2
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; NARROW-NEXT: pshufb %xmm1, %xmm2
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; NARROW-NEXT: movq %xmm2, (%edx,%eax,8)
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; NARROW-NEXT: incl (%esp)
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; NARROW-NEXT: .LBB0_1: # %forcond
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; NARROW-NEXT: # =>This Inner Loop Header: Depth=1
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; NARROW-NEXT: movl (%esp), %eax
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; NARROW-NEXT: cmpl {{[0-9]+}}(%esp), %eax
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; NARROW-NEXT: jl .LBB0_2
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; NARROW-NEXT: # BB#3: # %afterfor
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; NARROW-NEXT: addl $12, %esp
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; NARROW-NEXT: retl
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;
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; WIDE-LABEL: update:
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; WIDE: # BB#0: # %entry
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; WIDE-NEXT: subl $12, %esp
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; WIDE-NEXT: movl $0, (%esp)
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; WIDE-NEXT: pcmpeqd %xmm0, %xmm0
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; WIDE-NEXT: movdqa {{.*#+}} xmm1 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]
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; WIDE-NEXT: movdqa {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
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; WIDE-NEXT: jmp .LBB0_1
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; WIDE-NEXT: .p2align 4, 0x90
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; WIDE-NEXT: .LBB0_2: # %forbody
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; WIDE-NEXT: # in Loop: Header=BB0_1 Depth=1
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; WIDE-NEXT: movl (%esp), %eax
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; WIDE-NEXT: leal (,%eax,8), %ecx
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; WIDE-NEXT: movl {{[0-9]+}}(%esp), %edx
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; WIDE-NEXT: addl %ecx, %edx
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; WIDE-NEXT: movl %edx, {{[0-9]+}}(%esp)
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; WIDE-NEXT: addl {{[0-9]+}}(%esp), %ecx
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; WIDE-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; WIDE-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero
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; WIDE-NEXT: pinsrd $1, 4(%ecx,%eax,8), %xmm3
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; WIDE-NEXT: psubb %xmm0, %xmm3
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; WIDE-NEXT: psrlw $2, %xmm3
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; WIDE-NEXT: pand %xmm1, %xmm3
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; WIDE-NEXT: pxor %xmm2, %xmm3
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; WIDE-NEXT: psubb %xmm2, %xmm3
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; WIDE-NEXT: pextrd $1, %xmm3, 4(%edx,%eax,8)
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; WIDE-NEXT: movd %xmm3, (%edx,%eax,8)
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; WIDE-NEXT: incl (%esp)
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; WIDE-NEXT: .LBB0_1: # %forcond
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; WIDE-NEXT: # =>This Inner Loop Header: Depth=1
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; WIDE-NEXT: movl (%esp), %eax
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; WIDE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
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; WIDE-NEXT: jl .LBB0_2
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; WIDE-NEXT: # BB#3: # %afterfor
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; WIDE-NEXT: addl $12, %esp
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; WIDE-NEXT: retl
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entry:
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%dst_i.addr = alloca i64*
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%src_i.addr = alloca i64*
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%n.addr = alloca i32
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%i = alloca i32, align 4
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%dst = alloca <8 x i8>*, align 4
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%src = alloca <8 x i8>*, align 4
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store i64* %dst_i, i64** %dst_i.addr
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store i64* %src_i, i64** %src_i.addr
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store i32 %n, i32* %n.addr
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store i32 0, i32* %i
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br label %forcond
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forcond:
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%tmp = load i32, i32* %i
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%tmp1 = load i32, i32* %n.addr
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%cmp = icmp slt i32 %tmp, %tmp1
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br i1 %cmp, label %forbody, label %afterfor
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forbody:
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%tmp2 = load i32, i32* %i
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%tmp3 = load i64*, i64** %dst_i.addr
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%arrayidx = getelementptr i64, i64* %tmp3, i32 %tmp2
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%conv = bitcast i64* %arrayidx to <8 x i8>*
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store <8 x i8>* %conv, <8 x i8>** %dst
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%tmp4 = load i32, i32* %i
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%tmp5 = load i64*, i64** %src_i.addr
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%arrayidx6 = getelementptr i64, i64* %tmp5, i32 %tmp4
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%conv7 = bitcast i64* %arrayidx6 to <8 x i8>*
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store <8 x i8>* %conv7, <8 x i8>** %src
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%tmp8 = load i32, i32* %i
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%tmp9 = load <8 x i8>*, <8 x i8>** %dst
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%arrayidx10 = getelementptr <8 x i8>, <8 x i8>* %tmp9, i32 %tmp8
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%tmp11 = load i32, i32* %i
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%tmp12 = load <8 x i8>*, <8 x i8>** %src
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%arrayidx13 = getelementptr <8 x i8>, <8 x i8>* %tmp12, i32 %tmp11
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%tmp14 = load <8 x i8>, <8 x i8>* %arrayidx13
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%add = add <8 x i8> %tmp14, < i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1 >
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%shr = ashr <8 x i8> %add, < i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2 >
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store <8 x i8> %shr, <8 x i8>* %arrayidx10
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br label %forinc
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forinc:
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%tmp15 = load i32, i32* %i
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%inc = add i32 %tmp15, 1
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store i32 %inc, i32* %i
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br label %forcond
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afterfor:
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ret void
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}
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