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101 lines
3.8 KiB
LLVM
101 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse | FileCheck %s --check-prefix=X32-SSE --check-prefix=X32-SSE1
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32-SSE --check-prefix=X32-SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefix=X64-SSE --check-prefix=X64-SSE1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64-SSE --check-prefix=X64-SSE2
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; FNEG is defined as subtraction from -0.0.
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; This test verifies that we use an xor with a constant to flip the sign bits; no subtraction needed.
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define <4 x float> @t1(<4 x float> %Q) nounwind {
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; X32-SSE-LABEL: t1:
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; X32-SSE: # BB#0:
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; X32-SSE-NEXT: xorps .LCPI0_0, %xmm0
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; X32-SSE-NEXT: retl
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;
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; X64-SSE-LABEL: t1:
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; X64-SSE: # BB#0:
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; X64-SSE-NEXT: xorps {{.*}}(%rip), %xmm0
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; X64-SSE-NEXT: retq
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%tmp = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %Q
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ret <4 x float> %tmp
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}
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; This test verifies that we generate an FP subtraction because "0.0 - x" is not an fneg.
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define <4 x float> @t2(<4 x float> %Q) nounwind {
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; X32-SSE-LABEL: t2:
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; X32-SSE: # BB#0:
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; X32-SSE-NEXT: xorps %xmm1, %xmm1
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; X32-SSE-NEXT: subps %xmm0, %xmm1
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; X32-SSE-NEXT: movaps %xmm1, %xmm0
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; X32-SSE-NEXT: retl
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;
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; X64-SSE-LABEL: t2:
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; X64-SSE: # BB#0:
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; X64-SSE-NEXT: xorps %xmm1, %xmm1
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; X64-SSE-NEXT: subps %xmm0, %xmm1
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; X64-SSE-NEXT: movaps %xmm1, %xmm0
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; X64-SSE-NEXT: retq
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%tmp = fsub <4 x float> zeroinitializer, %Q
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ret <4 x float> %tmp
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}
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; If we're bitcasting an integer to an FP vector, we should avoid the FPU/vector unit entirely.
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; Make sure that we're flipping the sign bit and only the sign bit of each float.
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; So instead of something like this:
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; movd %rdi, %xmm0
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; xorps .LCPI2_0(%rip), %xmm0
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;
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; We should generate:
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; movabsq (put sign bit mask in integer register))
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; xorq (flip sign bits)
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; movd (move to xmm return register)
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define <2 x float> @fneg_bitcast(i64 %i) nounwind {
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; X32-SSE1-LABEL: fneg_bitcast:
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; X32-SSE1: # BB#0:
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; X32-SSE1-NEXT: pushl %ebp
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; X32-SSE1-NEXT: movl %esp, %ebp
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; X32-SSE1-NEXT: andl $-16, %esp
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; X32-SSE1-NEXT: subl $32, %esp
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; X32-SSE1-NEXT: movl $-2147483648, %eax # imm = 0xFFFFFFFF80000000
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; X32-SSE1-NEXT: movl 12(%ebp), %ecx
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; X32-SSE1-NEXT: xorl %eax, %ecx
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; X32-SSE1-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; X32-SSE1-NEXT: xorl 8(%ebp), %eax
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; X32-SSE1-NEXT: movl %eax, (%esp)
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; X32-SSE1-NEXT: movaps (%esp), %xmm0
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; X32-SSE1-NEXT: movl %ebp, %esp
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; X32-SSE1-NEXT: popl %ebp
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; X32-SSE1-NEXT: retl
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;
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; X32-SSE2-LABEL: fneg_bitcast:
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; X32-SSE2: # BB#0:
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; X32-SSE2-NEXT: movl $-2147483648, %eax # imm = 0xFFFFFFFF80000000
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; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-SSE2-NEXT: xorl %eax, %ecx
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; X32-SSE2-NEXT: xorl {{[0-9]+}}(%esp), %eax
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; X32-SSE2-NEXT: movd %eax, %xmm1
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; X32-SSE2-NEXT: movd %ecx, %xmm0
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; X32-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; X32-SSE2-NEXT: retl
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;
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; X64-SSE1-LABEL: fneg_bitcast:
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; X64-SSE1: # BB#0:
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; X64-SSE1-NEXT: movabsq $-9223372034707292160, %rax # imm = 0x8000000080000000
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; X64-SSE1-NEXT: xorq %rdi, %rax
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; X64-SSE1-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
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; X64-SSE1-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm0
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; X64-SSE1-NEXT: retq
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;
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; X64-SSE2-LABEL: fneg_bitcast:
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; X64-SSE2: # BB#0:
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; X64-SSE2-NEXT: movabsq $-9223372034707292160, %rax # imm = 0x8000000080000000
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; X64-SSE2-NEXT: xorq %rdi, %rax
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; X64-SSE2-NEXT: movd %rax, %xmm0
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; X64-SSE2-NEXT: retq
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%bitcast = bitcast i64 %i to <2 x float>
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%fneg = fsub <2 x float> <float -0.0, float -0.0>, %bitcast
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ret <2 x float> %fneg
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}
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