Craig Topper 95f0cd3953 [X86] Limit the number of target specific nodes emitted in LowerShiftParts ... The important part is the creation of the SHLD/SHRD nodes. The compare and the conditional move can use target independent nodes that can be legalized on their own. This gives some opportunities to trigger the optimizations present in the lowering for those things. And its just better to limit the number of places we emit target specific nodes. The changed test cases still aren't optimal. Differential Revision: https://reviews.llvm.org/D48619 llvm-svn: 335998		2018-06-29 17:24:07 +00:00
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AArch64	[MachineOutliner] Add always and never options to -enable-machine-outliner	2018-06-29 16:12:45 +00:00
AMDGPU	[AMDGPU] Enable LICM in the BE pipeline	2018-06-29 16:26:53 +00:00
ARC
ARM	[ARM] Parallel DSP Pass	2018-06-28 12:55:29 +00:00
AVR
BPF
Generic
Hexagon	[DAGCombiner] Ensure we use the correct CC result type in visitSDIV (REAPPLIED)	2018-06-28 17:33:41 +00:00
Inputs
Lanai
Mips	[mips] Support shrink-wrapping	2018-06-29 16:37:16 +00:00
MIR
MSP430
Nios2
NVPTX
PowerPC	[DAGCombiner] restrict (float)((int) f) --> ftrunc with no-signed-zeros	2018-06-27 18:16:40 +00:00
RISCV	[RISCV] Add machine function pass to merge base + offset	2018-06-27 20:51:42 +00:00
SPARC
SystemZ
Thumb
Thumb2
WebAssembly	[WebAssembly] Try fixing test/CodeGen/WebAssembly/vector_sdiv.ll	2018-06-27 19:35:50 +00:00
WinCFGuard
WinEH
X86	[X86] Limit the number of target specific nodes emitted in LowerShiftParts	2018-06-29 17:24:07 +00:00
XCore