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llvm-mirror/test/CodeGen/NVPTX/branch-fold.ll
Jingyue Wu e5794c4c5a Roll forward r242871
r242871 missed one place that should be guarded with isPhysicalReg. This patch
fixes that.

llvm-svn: 243555
2015-07-29 18:59:09 +00:00

41 lines
995 B
LLVM

; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 -disable-cgp | FileCheck %s
; Disable CGP which also folds branches, so that only BranchFolding is under
; the spotlight.
target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
target triple = "nvptx64-nvidia-cuda"
define void @foo(i32 %x, float* %output) {
; CHECK-LABEL: .visible .func foo(
; CHECK-NOT: bra.uni
; CHECK-NOT: LBB0_
%1 = icmp eq i32 %x, 1
br i1 %1, label %then, label %else
then:
br label %merge
else:
br label %merge
merge:
store float 2.0, float* %output
ret void
}
; PR24299. no crash
define ptx_kernel void @hoge() #0 {
; CHECK-LABEL: .visible .entry hoge(
bb:
br i1 undef, label %bb1, label %bb4
bb1: ; preds = %bb1, %bb
%tmp = phi i64 [ %tmp2, %bb1 ], [ undef, %bb ]
%tmp2 = add nsw i64 %tmp, 1
%tmp3 = icmp sle i64 %tmp, 0
br i1 %tmp3, label %bb1, label %bb4
bb4: ; preds = %bb4, %bb1, %bb
br label %bb4
}