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907a32660b
Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Eli Friedman llvm-svn: 325327
243 lines
5.1 KiB
LLVM
243 lines
5.1 KiB
LLVM
; RUN: llc -mtriple=thumb-eabi %s -verify-machineinstrs -o - | \
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; RUN: FileCheck %s -check-prefix CHECK --check-prefix CHECK-EABI
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; RUN: llc -mtriple=thumb-apple-darwin %s -verify-machineinstrs -o - | \
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; RUN: FileCheck %s -check-prefix CHECK -check-prefix CHECK-DARWIN
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define i64 @f1() {
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entry:
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ret i64 0
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; CHECK-LABEL: f1:
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; CHECK: movs r0, #0
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; CHECK: movs r1, r0
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}
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define i64 @f2() {
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entry:
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ret i64 1
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; CHECK-LABEL: f2:
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; CHECK: movs r0, #1
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; CHECK: movs r1, #0
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}
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define i64 @f3() {
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entry:
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ret i64 2147483647
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; CHECK-LABEL: f3:
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; CHECK: ldr r0,
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; CHECK: movs r1, #0
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}
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define i64 @f4() {
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entry:
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ret i64 2147483648
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; CHECK-LABEL: f4:
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; CHECK: movs r0, #1
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; CHECK: lsls r0, r0, #31
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; CHECK: movs r1, #0
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}
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define i64 @f5() {
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entry:
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ret i64 9223372036854775807
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; CHECK-LABEL: f5:
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; CHECK: movs r0, #0
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; CHECK: mvns r0, r0
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; CHECK: ldr r1,
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}
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define i64 @f6(i64 %x, i64 %y) {
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entry:
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%tmp1 = add i64 %y, 1 ; <i64> [#uses=1]
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ret i64 %tmp1
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; CHECK-LABEL: f6:
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; CHECK: movs r1, #0
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; CHECK: adds r0, r2, #1
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; CHECK: adcs r1, r3
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}
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define i64 @f6a(i64 %x, i64 %y) {
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entry:
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%tmp1 = add i64 %y, 10
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ret i64 %tmp1
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; CHECK-LABEL: f6a:
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; CHECK: movs r0, r2
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; CHECK: movs r1, #0
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; CHECK: adds r0, #10
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; CHECK: adcs r1, r3
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}
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define i64 @f6b(i64 %x, i64 %y) {
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entry:
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%tmp1 = add i64 %y, 1000
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ret i64 %tmp1
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; CHECK-LABEL: f6b:
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; CHECK: movs r0, #125
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; CHECK: lsls r0, r0, #3
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; CHECK: movs r1, #0
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; CHECK: adds r0, r2, r0
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; CHECK: adcs r1, r3
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}
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define void @f7() {
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entry:
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%tmp = call i64 @f8( ) ; <i64> [#uses=0]
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ret void
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; CHECK-LABEL: f7:
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; CHECK: bl
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}
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declare i64 @f8()
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define i64 @f9(i64 %a, i64 %b) {
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entry:
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%tmp = sub i64 %a, %b ; <i64> [#uses=1]
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ret i64 %tmp
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; CHECK-LABEL: f9:
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; CHECK: subs r0, r0, r2
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; CHECK: sbcs r1, r3
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}
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define i64 @f9a(i64 %x, i64 %y) { ; ADDC with small negative imm => SUBS imm
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entry:
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%tmp1 = sub i64 %y, 10
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ret i64 %tmp1
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; CHECK-LABEL: f9a:
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; CHECK: movs r1, r3
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; CHECK: movs r0, r2
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; CHECK: movs r2, #0
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; CHECK: subs r0, #10
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; CHECK: sbcs r1, r2
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}
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define i64 @f9b(i64 %x, i64 %y) { ; ADDC with big negative imm => SUBS reg
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entry:
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%tmp1 = sub i64 1000, %y
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ret i64 %tmp1
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; CHECK-LABEL: f9b:
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; CHECK: movs r0, #125
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; CHECK: lsls r0, r0, #3
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; CHECK: movs r1, #0
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; CHECK: subs r0, r0, r2
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; CHECK: sbcs r1, r3
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}
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define i64 @f9c(i64 %x, i32 %y) { ; SUBS with small positive imm => SUBS imm
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entry:
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%conv = sext i32 %y to i64
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%shl = shl i64 %conv, 32
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%or = or i64 %shl, 1
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%sub = sub nsw i64 %x, %or
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ret i64 %sub
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; CHECK-LABEL: f9c:
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; CHECK: subs r0, r0, #1
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; CHECK: sbcs r1, r2
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}
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define i64 @f9d(i64 %x, i32 %y) { ; SUBS with small negative imm => ADDS imm
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entry:
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%conv = sext i32 %y to i64
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%shl = shl i64 %conv, 32
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%or = or i64 %shl, 4294967295
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%sub = sub nsw i64 %x, %or
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ret i64 %sub
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; CHECK-LABEL: f9d:
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; CHECK: adds r0, r0, #1
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; CHECK: sbcs r1, r2
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}
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define i64 @f(i32 %a, i32 %b) {
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entry:
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%tmp = sext i32 %a to i64 ; <i64> [#uses=1]
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%tmp1 = sext i32 %b to i64 ; <i64> [#uses=1]
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%tmp2 = mul i64 %tmp1, %tmp ; <i64> [#uses=1]
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ret i64 %tmp2
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; CHECK-LABEL: f:
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; CHECK-V6: bl __aeabi_lmul
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; CHECK-DARWIN: __muldi3
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}
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define i64 @g(i32 %a, i32 %b) {
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entry:
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%tmp = zext i32 %a to i64 ; <i64> [#uses=1]
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%tmp1 = zext i32 %b to i64 ; <i64> [#uses=1]
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%tmp2 = mul i64 %tmp1, %tmp ; <i64> [#uses=1]
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ret i64 %tmp2
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; CHECK-LABEL: g:
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; CHECK-V6: bl __aeabi_lmul
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; CHECK-DARWIN: __muldi3
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}
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define i64 @f10() {
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entry:
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%a = alloca i64, align 8 ; <i64*> [#uses=1]
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%retval = load i64, i64* %a ; <i64> [#uses=1]
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ret i64 %retval
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; CHECK-LABEL: f10:
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; CHECK-EABI: sub sp, #8
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; CHECK-DARWIN: add r7, sp, #4
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; CHECK: ldr r0, [sp]
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; CHECK: ldr r1, [sp, #4]
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; CHECK-EABI: add sp, #8
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; CHECK-DARWIN: mov sp, r4
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}
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define i64 @f11(i64 %x, i64 %y) {
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entry:
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%tmp1 = add i64 -1000, %y
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%tmp2 = add i64 %tmp1, -1000
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ret i64 %tmp2
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; CHECK-LABEL: f11:
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; CHECK: movs r1, r3
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; CHECK: movs r0, #125
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; CHECK: lsls r0, r0, #3
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; CHECK: movs r3, #0
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; CHECK: subs r2, r2, r0
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; CHECK: sbcs r1, r3
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; CHECK: subs r0, r2, r0
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; CHECK: sbcs r1, r3
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}
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; "sub 2147483648" has to be lowered into "add -2147483648"
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define i64 @f12(i64 %x, i64 %y) {
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entry:
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%tmp1 = sub i64 %x, 2147483648
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ret i64 %tmp1
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; CHECK-LABEL: f12:
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; CHECK: movs r2, #1
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; CHECK: lsls r2, r2, #31
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; CHECK: movs r3, #0
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; CHECK: adds r0, r0, r2
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; CHECK: sbcs r1, r3
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}
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declare void @f13(i64 %x)
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define void @f14(i1 %x, i64 %y) #0 {
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; CHECK-LABEL: f14:
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entry:
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%a = add i64 %y, 47
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call void @f13(i64 %a)
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; CHECK: bl
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br i1 %x, label %if.end, label %if.then
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if.then:
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call void @f13(i64 %y)
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; CHECK: bl
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br label %if.end
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if.end:
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%b = add i64 %y, 45
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call void @f13(i64 %b)
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; CHECK: adds
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; CHECK: adcs
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; CHECK: bl
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%c = add i64 %y, 47
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call void @f13(i64 %c)
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; CHECK: adds
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; CHECK-NEXT: adcs
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; CHECK: bl
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ret void
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}
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attributes #0 = { optsize }
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