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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
48 lines
1.5 KiB
LLVM
48 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64
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define i32 @PR22970_i32(i32* nocapture readonly, i32) {
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; X86-LABEL: PR22970_i32:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl $4095, %ecx # imm = 0xFFF
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; X86-NEXT: andl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl 32(%eax,%ecx,4), %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: PR22970_i32:
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; X64: # %bb.0:
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; X64-NEXT: # kill: def $esi killed $esi def $rsi
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; X64-NEXT: andl $4095, %esi # imm = 0xFFF
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; X64-NEXT: movl 32(%rdi,%rsi,4), %eax
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; X64-NEXT: retq
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%3 = and i32 %1, 4095
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%4 = add nuw nsw i32 %3, 8
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%5 = zext i32 %4 to i64
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%6 = getelementptr inbounds i32, i32* %0, i64 %5
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%7 = load i32, i32* %6, align 4
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ret i32 %7
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}
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define i32 @PR22970_i64(i32* nocapture readonly, i64) {
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; X86-LABEL: PR22970_i64:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl $4095, %ecx # imm = 0xFFF
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; X86-NEXT: andl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl 32(%eax,%ecx,4), %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: PR22970_i64:
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; X64: # %bb.0:
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; X64-NEXT: andl $4095, %esi # imm = 0xFFF
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; X64-NEXT: movl 32(%rdi,%rsi,4), %eax
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; X64-NEXT: retq
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%3 = and i64 %1, 4095
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%4 = add nuw nsw i64 %3, 8
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%5 = getelementptr inbounds i32, i32* %0, i64 %4
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%6 = load i32, i32* %5, align 4
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ret i32 %6
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}
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