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e6ef9c7af1
For Thumb2, we prefer low regs (costPerUse = 0) to allow narrow encoding. However, current allocation order is like: R0-R3, R12, LR, R4-R11 As a result, a lot of instructs that use R12/LR will be wide instrs. This patch changes the allocation order to: R0-R7, R12, LR, R8-R11 for thumb2 and -Osize. In most cases, there is no extra push/pop instrs as they will be folded into existing ones. There might be slight performance impact due to more stack usage, so we only enable it when opt for min size. https://reviews.llvm.org/D30324 llvm-svn: 365014
30 lines
887 B
LLVM
30 lines
887 B
LLVM
; REQUIRES: asserts
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; RUN: llc -debug-only=regalloc < %s 2>%t | FileCheck %s --check-prefix=CHECK
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; RUN: FileCheck %s < %t --check-prefix=DEBUG
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n8:16:32-S64"
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target triple = "thumbv7m--linux-gnueabi"
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; DEBUG: AllocationOrder(GPR) = [ $r0 $r1 $r2 $r3 $r4 $r5 $r6 $r7 $r12 $lr $r8 $r9 $r10 $r11 ]
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define i32 @test_minsize(i32 %x) optsize minsize {
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; CHECK-LABEL: test_minsize:
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entry:
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; CHECK: mov r4, r0
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tail call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3}"()
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; CHECK: mov r0, r4
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ret i32 %x
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}
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; DEBUG: AllocationOrder(GPR) = [ $r0 $r1 $r2 $r3 $r12 $lr $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 ]
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define i32 @test_optsize(i32 %x) optsize {
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; CHECK-LABEL: test_optsize:
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entry:
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; CHECK: mov r12, r0
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tail call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3}"()
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; CHECK: mov r0, r12
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ret i32 %x
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}
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