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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 19:23:23 +01:00
llvm-mirror/test/CodeGen
2019-12-17 07:04:19 +00:00
..
AArch64 [AArch64][SVE] Add patterns for logical immediate operations. 2019-12-16 16:18:34 -05:00
AMDGPU Fix for AMDGPU MUL_I24 known bits calculation 2019-12-16 10:25:57 +00:00
ARC
ARM [PGO][PGSO] Enable size optimizations in code gen / target passes for cold code. 2019-12-13 11:01:19 -08:00
AVR
BPF [BPF] put not-section-attribute externs into BTF ".extern" data section 2019-12-10 11:45:17 -08:00
Generic
Hexagon
Inputs
Lanai
Mips [Mips] Add support for min/max/umin/umax atomics 2019-12-12 11:32:37 +01:00
MIR [llvm][MIRVRegNamerUtils] Adding hashing on CImm / FPImm MachineOperands. 2019-12-16 18:25:04 -05:00
MSP430
NVPTX
PowerPC [NFC][Test][PowerPC] Add the test to verify the mask with constant 2019-12-17 07:04:19 +00:00
RISCV [PGO][PGSO] Enable size optimizations in code gen / target passes for cold code. 2019-12-13 11:01:19 -08:00
SPARC
SystemZ [SystemZ] Improve verification of MachineOperands. 2019-12-16 09:51:54 -08:00
Thumb
Thumb2 [ARM][MVE][Intrinsics] All vqdmulhq/vqrdmulhq tests should be for signed numbers. 2019-12-13 17:29:59 +00:00
WebAssembly [WebAssembly] Replace SIMD int min/max builtins with patterns 2019-12-16 11:48:49 -08:00
WinCFGuard
WinEH
X86 Honor -fuse-init-array when os is not specified on x86 2019-12-16 15:21:23 -08:00
XCore