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7cd663b80c
Generally, the ISEL is expanded into if-then-else sequence, in some cases (like when the destination register is the same with the true or false value register), it may just be expanded into just the if or else sequence. llvm-svn: 292154
200 lines
5.2 KiB
LLVM
200 lines
5.2 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Function Attrs: nounwind readnone
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define zeroext i1 @test1(float %v1, float %v2) #0 {
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entry:
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%cmp = fcmp oge float %v1, %v2
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%cmp2 = fcmp ole float %v2, 0.000000e+00
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%and5 = and i1 %cmp, %cmp2
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ret i1 %and5
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; CHECK-LABEL: @test1
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; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
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; CHECK-DAG: li [[REG1:[0-9]+]], 1
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; CHECK-DAG: xxlxor [[REG2:[0-9]+]], [[REG2]], [[REG2]]
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; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]]
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; CHECK: crnor
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; CHECK: crnor
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; CHECK: crnand [[REG4:[0-9]+]],
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; CHECK: isel 3, 0, [[REG1]], [[REG4]]
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; CHECK-NO-ISEL-LABEL: @test1
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; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
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; CHECK-NO-ISEL-NEXT: blr
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; CHECK-NO-ISEL-NEXT: [[TRUE]]
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; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
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; CHECK-NO-ISEL-NEXT: blr
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; CHECK: blr
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}
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; Function Attrs: nounwind readnone
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define zeroext i1 @test2(float %v1, float %v2) #0 {
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entry:
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%cmp = fcmp oge float %v1, %v2
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%cmp2 = fcmp ole float %v2, 0.000000e+00
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%xor5 = xor i1 %cmp, %cmp2
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ret i1 %xor5
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; CHECK-LABEL: @test2
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; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
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; CHECK-DAG: li [[REG1:[0-9]+]], 1
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; CHECK-DAG: xxlxor [[REG2:[0-9]+]], [[REG2]], [[REG2]]
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; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]]
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; CHECK: crnor
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; CHECK: crnor
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; CHECK: creqv [[REG4:[0-9]+]],
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; CHECK: isel 3, 0, [[REG1]], [[REG4]]
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; CHECK: blr
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}
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; Function Attrs: nounwind readnone
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define zeroext i1 @test3(float %v1, float %v2, i32 signext %x) #0 {
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entry:
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%cmp = fcmp oge float %v1, %v2
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%cmp2 = fcmp ole float %v2, 0.000000e+00
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%cmp4 = icmp ne i32 %x, -2
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%and7 = and i1 %cmp2, %cmp4
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%xor8 = xor i1 %cmp, %and7
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ret i1 %xor8
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; CHECK-LABEL: @test3
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; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
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; CHECK-DAG: li [[REG1:[0-9]+]], 1
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; CHECK-DAG: xxlxor [[REG2:[0-9]+]], [[REG2]], [[REG2]]
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; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]]
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; CHECK: crnor
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; CHECK: crnor
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; CHECK: crandc
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; CHECK: creqv [[REG4:[0-9]+]],
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; CHECK: isel 3, 0, [[REG1]], [[REG4]]
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; CHECK: blr
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}
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; Function Attrs: nounwind readnone
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define zeroext i1 @test4(i1 zeroext %v1, i1 zeroext %v2, i1 zeroext %v3) #0 {
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entry:
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%and8 = and i1 %v1, %v2
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%or9 = or i1 %and8, %v3
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ret i1 %or9
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; CHECK-DAG: @test4
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; CHECK: and [[REG1:[0-9]+]], 3, 4
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; CHECK: or 3, [[REG1]], 5
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; CHECK: blr
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}
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; Function Attrs: nounwind readnone
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define zeroext i1 @test5(i1 zeroext %v1, i1 zeroext %v2, i32 signext %v3) #0 {
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entry:
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%and6 = and i1 %v1, %v2
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%cmp = icmp ne i32 %v3, -2
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%or7 = or i1 %and6, %cmp
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ret i1 %or7
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; CHECK-LABEL: @test5
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; CHECK-DAG: and [[REG1:[0-9]+]], 3, 4
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; CHECK-DAG: cmpwi {{[0-9]+}}, 5, -2
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; CHECK-DAG: li [[REG3:[0-9]+]], 1
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; CHECK-DAG: andi. {{[0-9]+}}, [[REG1]], 1
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; CHECK-DAG: crandc [[REG5:[0-9]+]],
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; CHECK: isel 3, 0, [[REG3]], [[REG5]]
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; CHECK: blr
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}
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; Function Attrs: nounwind readnone
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define zeroext i1 @test6(i1 zeroext %v1, i1 zeroext %v2, i32 signext %v3) #0 {
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entry:
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%cmp = icmp ne i32 %v3, -2
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%or6 = or i1 %cmp, %v2
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%and7 = and i1 %or6, %v1
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ret i1 %and7
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; CHECK-LABEL: @test6
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; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
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; CHECK-DAG: cmpwi {{[0-9]+}}, 5, -2
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; CHECK-DAG: crmove [[REG1:[0-9]+]], 1
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; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
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; CHECK-DAG: li [[REG2:[0-9]+]], 1
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; CHECK-DAG: crorc [[REG4:[0-9]+]], 1,
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; CHECK-DAG: crnand [[REG5:[0-9]+]], [[REG4]], [[REG1]]
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; CHECK: isel 3, 0, [[REG2]], [[REG5]]
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; CHECK: blr
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}
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; Function Attrs: nounwind readnone
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define signext i32 @test7(i1 zeroext %v2, i32 signext %i1, i32 signext %i2) #0 {
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entry:
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%cond = select i1 %v2, i32 %i1, i32 %i2
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ret i32 %cond
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; CHECK-LABEL: @test7
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; CHECK: andi. {{[0-9]+}}, 3, 1
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; CHECK: isel 3, 4, 5, 1
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; CHECK: blr
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}
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define signext i32 @exttest7(i32 signext %a) #0 {
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entry:
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%cmp = icmp eq i32 %a, 5
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%cond = select i1 %cmp, i32 7, i32 8
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ret i32 %cond
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; CHECK-LABEL: @exttest7
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; CHECK-DAG: cmplwi {{[0-9]+}}, 3, 5
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; CHECK-DAG: li [[REG1:[0-9]+]], 8
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; CHECK-DAG: li [[REG2:[0-9]+]], 7
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; CHECK: isel 3, [[REG2]], [[REG1]],
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; CHECK-NOT: rldicl
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; CHECK: blr
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}
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define zeroext i32 @exttest8() #0 {
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entry:
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%v0 = load i64, i64* undef, align 8
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%sub = sub i64 80, %v0
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%div = lshr i64 %sub, 1
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%conv13 = trunc i64 %div to i32
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%cmp14 = icmp ugt i32 %conv13, 80
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%.conv13 = select i1 %cmp14, i32 0, i32 %conv13
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ret i32 %.conv13
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; CHECK-LABEL: @exttest8
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; This is a don't-crash test: %conv13 is both one of the possible select output
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; values and also an input to the conditional feeding it.
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}
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; Function Attrs: nounwind readnone
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define float @test8(i1 zeroext %v2, float %v1, float %v3) #0 {
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entry:
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%cond = select i1 %v2, float %v1, float %v3
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ret float %cond
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; CHECK-LABEL: @test8
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; CHECK: andi. {{[0-9]+}}, 3, 1
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; CHECK: bclr 12, 1, 0
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; CHECK: fmr 1, 2
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; CHECK: blr
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}
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; Function Attrs: nounwind readnone
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define signext i32 @test10(i32 signext %v1, i32 signext %v2) #0 {
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entry:
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%tobool = icmp ne i32 %v1, 0
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%lnot = icmp eq i32 %v2, 0
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%and3 = and i1 %tobool, %lnot
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%and = zext i1 %and3 to i32
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ret i32 %and
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; CHECK-LABEL: @test10
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; CHECK-DAG: cmpwi {{[0-9]+}}, 3, 0
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; CHECK-DAG: cmpwi {{[0-9]+}}, 4, 0
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; CHECK-DAG: li [[REG2:[0-9]+]], 1
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; CHECK-DAG: crorc [[REG3:[0-9]+]],
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; CHECK: isel 3, 0, [[REG2]], [[REG3]]
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; CHECK: blr
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}
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attributes #0 = { nounwind readnone }
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