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llvm-mirror/test/CodeGen
Cong Hou 96c5c49122 Enhance loop rotation with existence of profile data in MachineBlockPlacement pass.
Currently, in MachineBlockPlacement pass the loop is rotated to let the best exit to be the last BB in the loop chain, to maximize the fall-through from the loop to outside. With profile data, we can determine the cost in terms of missed fall through opportunities when rotating a loop chain and select the best rotation. Basically, there are three kinds of cost to consider for each rotation:

1. The possibly missed fall through edge (if it exists) from BB out of the loop to the loop header.
2. The possibly missed fall through edges (if they exist) from the loop exits to BB out of the loop.
3. The missed fall through edge (if it exists) from the last BB to the first BB in the loop chain.

Therefore, the cost for a given rotation is the sum of costs listed above. We select the best rotation with the smallest cost. This is only for PGO mode when we have more precise edge frequencies.

Differential revision: http://reviews.llvm.org/D10717

llvm-svn: 250754
2015-10-19 23:16:40 +00:00
..
AArch64 [AArch64]Merge halfword loads into a 32-bit load 2015-10-19 18:34:53 +00:00
AMDGPU DAGCombiner: Don't stop finding better chain on 2 aliases 2015-10-13 00:49:00 +00:00
ARM Fix mapping of @llvm.arm.ssat/usat intrinsics to ssat/usat instructions 2015-10-19 11:44:24 +00:00
BPF [bpf] Do not expand UNDEF SDNode during insn selection lowering 2015-10-08 18:52:40 +00:00
CPP
Generic [Hexagon] Reverting test file change. 2015-10-17 01:58:51 +00:00
Hexagon [Hexagon] Delay emission of CFI instructions 2015-10-19 17:46:01 +00:00
Inputs
Mips [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
MIR [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. 2015-10-15 14:34:23 +00:00
MSP430
NVPTX
PowerPC [MachO] Stop generating *coal* sections. 2015-10-15 05:28:38 +00:00
SPARC Fix assert when emitting llvm.pow.f86. 2015-10-09 21:36:19 +00:00
SystemZ [SystemZ] CodeGen/SystemZ/asm-18.ll run with -verify-machineinstrs 2015-10-10 07:20:23 +00:00
Thumb [ARM] Modify codegen for memcpy intrinsic to prefer LDM/STM. 2015-10-05 14:49:54 +00:00
Thumb2 [ARM] Use correct half-precision functions in EABI mode 2015-10-07 16:58:49 +00:00
WebAssembly WebAssembly: don't omit dead vregs from locals 2015-10-17 00:25:38 +00:00
WinEH [WinEH] Fix eh.exceptionpointer intrinsic lowering 2015-10-17 00:08:08 +00:00
X86 Enhance loop rotation with existence of profile data in MachineBlockPlacement pass. 2015-10-19 23:16:40 +00:00
XCore