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c09f6fd5ff
Summary: This patch adds the following SVE intrinsics for scatter stores: * 64-bit offsets: * @llvm.aarch64.sve.st1.scatter (unscaled) * @llvm.aarch64.sve.st1.scatter.index (scaled) * 32-bit unscaled offsets: * @llvm.aarch64.sve.st1.scatter.uxtw (zero-extended offset) * @llvm.aarch64.sve.st1.scatter.sxtw (sign-extended-offset) * 32-bit scaled offsets: * @llvm.aarch64.sve.st1.scatter.uxtw.index (zero-extended offset) * @llvm.aarch64.sve.st1.scatter.sxtw.index (sign-extended offset) * vector base + immediate: * @llvm.aarch64.sve.st1.scatter.imm Reviewers: rengolin, efriedma, sdesmalen Reviewed By: efriedma, sdesmalen Subscribers: kmclaughlin, eli.friedman, tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71074
134 lines
6.4 KiB
LLVM
134 lines
6.4 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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;
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; ST1B, ST1W, ST1H, ST1D: vector + immediate (index)
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; e.g. st1h { z0.s }, p0, [z1.s, #16]
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;
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; ST1B
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define void @sst1b_s_imm(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %base) {
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; CHECK-LABEL: sst1b_s_imm:
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; CHECK: st1b { z0.s }, p0, [z1.s, #16]
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; CHECK-NEXT: ret
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%data_trunc = trunc <vscale x 4 x i32> %data to <vscale x 4 x i8>
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call void @llvm.aarch64.sve.st1.scatter.imm.nxv4i8.nxv4i32(<vscale x 4 x i8> %data_trunc,
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<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %base,
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i64 16)
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ret void
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}
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define void @sst1b_d_imm(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %base) {
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; CHECK-LABEL: sst1b_d_imm:
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; CHECK: st1b { z0.d }, p0, [z1.d, #16]
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; CHECK-NEXT: ret
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%data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i8>
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call void @llvm.aarch64.sve.st1.scatter.imm.nxv2i8.nxv2i64(<vscale x 2 x i8> %data_trunc,
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<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %base,
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i64 16)
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ret void
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}
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; ST1H
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define void @sst1h_s_imm(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %base) {
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; CHECK-LABEL: sst1h_s_imm:
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; CHECK: st1h { z0.s }, p0, [z1.s, #16]
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; CHECK-NEXT: ret
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%data_trunc = trunc <vscale x 4 x i32> %data to <vscale x 4 x i16>
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call void @llvm.aarch64.sve.st1.scatter.imm.nxv4i16.nxv4i32(<vscale x 4 x i16> %data_trunc,
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<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %base,
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i64 16)
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ret void
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}
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define void @sst1h_d_imm(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %base) {
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; CHECK-LABEL: sst1h_d_imm:
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; CHECK: st1h { z0.d }, p0, [z1.d, #16]
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; CHECK-NEXT: ret
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%data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16>
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call void @llvm.aarch64.sve.st1.scatter.imm.nxv2i16.nxv2i64(<vscale x 2 x i16> %data_trunc,
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<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %base,
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i64 16)
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ret void
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}
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; ST1W
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define void @sst1w_s_imm(<vscale x 4 x i32> %data, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %base) {
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; CHECK-LABEL: sst1w_s_imm:
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; CHECK: st1w { z0.s }, p0, [z1.s, #16]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st1.scatter.imm.nxv4i32.nxv4i32(<vscale x 4 x i32> %data,
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<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %base,
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i64 16)
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ret void
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}
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define void @sst1w_d_imm(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %base) {
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; CHECK-LABEL: sst1w_d_imm:
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; CHECK: st1w { z0.d }, p0, [z1.d, #16]
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; CHECK-NEXT: ret
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%data_trunc = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32>
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call void @llvm.aarch64.sve.st1.scatter.imm.nxv2i32.nxv2i64(<vscale x 2 x i32> %data_trunc,
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<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %base,
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i64 16)
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ret void
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}
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define void @sst1w_s_imm_float(<vscale x 4 x float> %data, <vscale x 4 x i1> %pg, <vscale x 4 x i32> %base) {
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; CHECK-LABEL: sst1w_s_imm_float:
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; CHECK: st1w { z0.s }, p0, [z1.s, #16]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st1.scatter.imm.nxv4f32.nxv4i32(<vscale x 4 x float> %data,
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<vscale x 4 x i1> %pg,
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<vscale x 4 x i32> %base,
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i64 16)
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ret void
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}
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; ST1D
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define void @sst1d_d_imm(<vscale x 2 x i64> %data, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %base) {
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; CHECK-LABEL: sst1d_d_imm:
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; CHECK: st1d { z0.d }, p0, [z1.d, #16]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st1.scatter.imm.nxv2i64.nxv2i64(<vscale x 2 x i64> %data,
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<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %base,
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i64 16)
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ret void
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}
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define void @sst1d_d_imm_double(<vscale x 2 x double> %data, <vscale x 2 x i1> %pg, <vscale x 2 x i64> %base) {
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; CHECK-LABEL: sst1d_d_imm_double:
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; CHECK: st1d { z0.d }, p0, [z1.d, #16]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.st1.scatter.imm.nxv2f64.nxv2i64(<vscale x 2 x double> %data,
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<vscale x 2 x i1> %pg,
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<vscale x 2 x i64> %base,
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i64 16)
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ret void
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}
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; ST1B
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declare void @llvm.aarch64.sve.st1.scatter.imm.nxv4i8.nxv4i32(<vscale x 4 x i8>, <vscale x 4 x i1>, <vscale x 4 x i32>, i64)
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declare void @llvm.aarch64.sve.st1.scatter.imm.nxv2i8.nxv2i64(<vscale x 2 x i8>, <vscale x 2 x i1>, <vscale x 2 x i64>, i64)
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; ST1H
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declare void @llvm.aarch64.sve.st1.scatter.imm.nxv4i16.nxv4i32(<vscale x 4 x i16>, <vscale x 4 x i1>, <vscale x 4 x i32>, i64)
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declare void @llvm.aarch64.sve.st1.scatter.imm.nxv2i16.nxv2i64(<vscale x 2 x i16>, <vscale x 2 x i1>, <vscale x 2 x i64>, i64)
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; ST1W
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declare void @llvm.aarch64.sve.st1.scatter.imm.nxv4i32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>, i64)
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declare void @llvm.aarch64.sve.st1.scatter.imm.nxv2i32.nxv2i64(<vscale x 2 x i32>, <vscale x 2 x i1>, <vscale x 2 x i64>, i64)
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declare void @llvm.aarch64.sve.st1.scatter.imm.nxv4f32.nxv4i32(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x i32>, i64)
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; ST1D
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declare void @llvm.aarch64.sve.st1.scatter.imm.nxv2i64.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>, i64)
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declare void @llvm.aarch64.sve.st1.scatter.imm.nxv2f64.nxv2i64(<vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x i64>, i64)
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