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llvm-mirror/test/CodeGen
Chad Rosier 9733d5cead [AArch64] Add SchedRW lists to NEON instructions.
Previously, only regular AArch64 instructions were annotated with SchedRW lists.
This patch does the same for NEON enabling these instructions to be scheduled by
the MIScheduler. Additionally, store operations are now modeled and a few
SchedRW lists were updated for bug fixes (e.g. multiple def operands).

Reviewers: apazos, mcrosier, atrick
Patch by Dave Estes <cestes@codeaurora.org>!

llvm-svn: 204505
2014-03-21 19:34:41 +00:00
..
AArch64 [AArch64] Add SchedRW lists to NEON instructions. 2014-03-21 19:34:41 +00:00
ARM Fix test command line to avoid generating output file. 2014-03-21 07:20:29 +00:00
CPP Begin adding docs and IR-level support for the inalloca attribute 2013-12-19 02:14:12 +00:00
Generic CommandLine: Exit successfully for -version and -help 2014-02-28 19:08:01 +00:00
Hexagon Fix broken CHECK lines 2014-02-16 07:31:05 +00:00
Inputs Debug Info: update testing cases to specify the debug info version number. 2013-11-22 21:49:45 +00:00
Mips [mips] Correct lowering of VECTOR_SHUFFLE to VSHF. 2014-03-21 16:56:51 +00:00
MSP430 Fix known typos 2014-01-24 17:20:08 +00:00
NVPTX Expose "noduplicate" attribute as a property for intrinsics. 2014-03-18 23:51:07 +00:00
PowerPC Remove redundant test. 2014-03-21 18:00:51 +00:00
R600 R600/SI: Move instruction patterns to scalar versions. 2014-03-21 18:01:18 +00:00
SPARC Remove the linker_private and linker_private_weak linkages. 2014-03-13 23:18:37 +00:00
SystemZ [SystemZ] Add support for z196 float<->unsigned conversions 2014-03-21 10:56:30 +00:00
Thumb Add triples to try to fix the windows bots. 2014-02-13 16:49:47 +00:00
Thumb2 ARMv8 IfConversion must skip narrow instructions that a) define CPSR and b) wouldn't affect CPSR in an IT block 2014-02-26 11:27:28 +00:00
X86 Move codegen test over to MC. 2014-03-21 17:55:34 +00:00
XCore [XCore] Add support for the "m" inline asm constraint. 2014-03-06 16:37:48 +00:00