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ef448d0349
This patch contains a pass that transforms CBZ/CBNZ/TBZ/TBNZ instructions into a conditional branch (Bcc), when the NZCV flags can be set for "free". This is preferred on targets that have more flexibility when scheduling Bcc instructions as compared to CBZ/CBNZ/TBZ/TBNZ (assuming all other variables are equal). This can reduce register pressure and is also the default behavior for GCC. A few examples: add w8, w0, w1 -> cmn w0, w1 ; CMN is an alias of ADDS. cbz w8, .LBB_2 -> b.eq .LBB0_2 ; single def/use of w8 removed. add w8, w0, w1 -> adds w8, w0, w1 ; w8 has multiple uses. cbz w8, .LBB1_2 -> b.eq .LBB1_2 sub w8, w0, w1 -> subs w8, w0, w1 ; w8 has multiple uses. tbz w8, #31, .LBB6_2 -> b.ge .LBB6_2 In looking at all current sub-target machine descriptions, this transformation appears to be either positive or neutral. Differential Revision: https://reviews.llvm.org/D34220. llvm-svn: 306144
73 lines
2.8 KiB
C++
73 lines
2.8 KiB
C++
//==-- AArch64.h - Top-level interface for AArch64 --------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in the LLVM
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// AArch64 back-end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64_H
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#include "MCTargetDesc/AArch64MCTargetDesc.h"
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#include "Utils/AArch64BaseInfo.h"
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#include "llvm/Support/DataTypes.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class AArch64RegisterBankInfo;
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class AArch64Subtarget;
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class AArch64TargetMachine;
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class FunctionPass;
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class InstructionSelector;
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class MachineFunctionPass;
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FunctionPass *createAArch64DeadRegisterDefinitions();
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FunctionPass *createAArch64RedundantCopyEliminationPass();
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FunctionPass *createAArch64CondBrTuning();
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FunctionPass *createAArch64ConditionalCompares();
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FunctionPass *createAArch64AdvSIMDScalar();
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FunctionPass *createAArch64ISelDag(AArch64TargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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FunctionPass *createAArch64StorePairSuppressPass();
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FunctionPass *createAArch64ExpandPseudoPass();
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FunctionPass *createAArch64LoadStoreOptimizationPass();
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FunctionPass *createAArch64VectorByElementOptPass();
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ModulePass *createAArch64PromoteConstantPass();
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FunctionPass *createAArch64ConditionOptimizerPass();
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FunctionPass *createAArch64A57FPLoadBalancing();
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FunctionPass *createAArch64A53Fix835769();
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FunctionPass *createAArch64CleanupLocalDynamicTLSPass();
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FunctionPass *createAArch64CollectLOHPass();
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InstructionSelector *
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createAArch64InstructionSelector(const AArch64TargetMachine &,
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AArch64Subtarget &, AArch64RegisterBankInfo &);
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void initializeAArch64A53Fix835769Pass(PassRegistry&);
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void initializeAArch64A57FPLoadBalancingPass(PassRegistry&);
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void initializeAArch64AdvSIMDScalarPass(PassRegistry&);
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void initializeAArch64CollectLOHPass(PassRegistry&);
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void initializeAArch64CondBrTuningPass(PassRegistry &);
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void initializeAArch64ConditionalComparesPass(PassRegistry&);
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void initializeAArch64ConditionOptimizerPass(PassRegistry&);
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void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry&);
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void initializeAArch64ExpandPseudoPass(PassRegistry&);
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void initializeAArch64LoadStoreOptPass(PassRegistry&);
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void initializeAArch64VectorByElementOptPass(PassRegistry&);
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void initializeAArch64PromoteConstantPass(PassRegistry&);
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void initializeAArch64RedundantCopyEliminationPass(PassRegistry&);
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void initializeAArch64StorePairSuppressPass(PassRegistry&);
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void initializeLDTLSCleanupPass(PassRegistry&);
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} // end namespace llvm
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#endif
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