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This gives DAG patterns matching indexed patterns where either side is an indexed vector. llvm-svn: 206875
125 lines
4.2 KiB
LLVM
125 lines
4.2 KiB
LLVM
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
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; arm64 has separate copy due to intrinsics (aarch64-neon-scalar-by-elem-mul.ll)
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define float @test_fmul_lane_ss2S(float %a, <2 x float> %v) {
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; CHECK: test_fmul_lane_ss2S
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; CHECK: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
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%tmp1 = extractelement <2 x float> %v, i32 1
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%tmp2 = fmul float %a, %tmp1;
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ret float %tmp2;
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}
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define float @test_fmul_lane_ss2S_swap(float %a, <2 x float> %v) {
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; CHECK: test_fmul_lane_ss2S_swap
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; CHECK: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
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%tmp1 = extractelement <2 x float> %v, i32 1
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%tmp2 = fmul float %tmp1, %a;
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ret float %tmp2;
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}
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define float @test_fmul_lane_ss4S(float %a, <4 x float> %v) {
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; CHECK: test_fmul_lane_ss4S
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; CHECK: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
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%tmp1 = extractelement <4 x float> %v, i32 3
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%tmp2 = fmul float %a, %tmp1;
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ret float %tmp2;
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}
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define float @test_fmul_lane_ss4S_swap(float %a, <4 x float> %v) {
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; CHECK: test_fmul_lane_ss4S_swap
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; CHECK: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
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%tmp1 = extractelement <4 x float> %v, i32 3
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%tmp2 = fmul float %tmp1, %a;
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ret float %tmp2;
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}
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define double @test_fmul_lane_ddD(double %a, <1 x double> %v) {
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; CHECK: test_fmul_lane_ddD
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; CHECK: fmul {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
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%tmp1 = extractelement <1 x double> %v, i32 0
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%tmp2 = fmul double %a, %tmp1;
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ret double %tmp2;
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}
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define double @test_fmul_lane_dd2D(double %a, <2 x double> %v) {
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; CHECK: test_fmul_lane_dd2D
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; CHECK: fmul {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
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%tmp1 = extractelement <2 x double> %v, i32 1
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%tmp2 = fmul double %a, %tmp1;
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ret double %tmp2;
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}
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define double @test_fmul_lane_dd2D_swap(double %a, <2 x double> %v) {
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; CHECK: test_fmul_lane_dd2D_swap
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; CHECK: fmul {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
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%tmp1 = extractelement <2 x double> %v, i32 1
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%tmp2 = fmul double %tmp1, %a;
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ret double %tmp2;
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}
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declare float @llvm.aarch64.neon.vmulx.f32(float, float)
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define float @test_fmulx_lane_f32(float %a, <2 x float> %v) {
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; CHECK: test_fmulx_lane_f32
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; CHECK: fmulx {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
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%tmp1 = extractelement <2 x float> %v, i32 1
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%tmp2 = call float @llvm.aarch64.neon.vmulx.f32(float %a, float %tmp1)
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ret float %tmp2;
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}
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define float @test_fmulx_laneq_f32(float %a, <4 x float> %v) {
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; CHECK: test_fmulx_laneq_f32
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; CHECK: fmulx {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
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%tmp1 = extractelement <4 x float> %v, i32 3
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%tmp2 = call float @llvm.aarch64.neon.vmulx.f32(float %a, float %tmp1)
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ret float %tmp2;
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}
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define float @test_fmulx_laneq_f32_swap(float %a, <4 x float> %v) {
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; CHECK: test_fmulx_laneq_f32_swap
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; CHECK: fmulx {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
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%tmp1 = extractelement <4 x float> %v, i32 3
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%tmp2 = call float @llvm.aarch64.neon.vmulx.f32(float %tmp1, float %a)
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ret float %tmp2;
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}
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declare double @llvm.aarch64.neon.vmulx.f64(double, double)
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define double @test_fmulx_lane_f64(double %a, <1 x double> %v) {
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; CHECK: test_fmulx_lane_f64
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; CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
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%tmp1 = extractelement <1 x double> %v, i32 0
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%tmp2 = call double @llvm.aarch64.neon.vmulx.f64(double %a, double %tmp1)
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ret double %tmp2;
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}
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define double @test_fmulx_laneq_f64_0(double %a, <2 x double> %v) {
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; CHECK: test_fmulx_laneq_f64_0
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; CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
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%tmp1 = extractelement <2 x double> %v, i32 0
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%tmp2 = call double @llvm.aarch64.neon.vmulx.f64(double %a, double %tmp1)
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ret double %tmp2;
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}
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define double @test_fmulx_laneq_f64_1(double %a, <2 x double> %v) {
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; CHECK: test_fmulx_laneq_f64_1
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; CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
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%tmp1 = extractelement <2 x double> %v, i32 1
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%tmp2 = call double @llvm.aarch64.neon.vmulx.f64(double %a, double %tmp1)
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ret double %tmp2;
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}
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define double @test_fmulx_laneq_f64_1_swap(double %a, <2 x double> %v) {
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; CHECK: test_fmulx_laneq_f64_1_swap
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; CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
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%tmp1 = extractelement <2 x double> %v, i32 1
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%tmp2 = call double @llvm.aarch64.neon.vmulx.f64(double %tmp1, double %a)
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ret double %tmp2;
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}
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