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9759e898f0
on llvmdev: SRoA is introducing MMX datatypes like <1 x i64>, which then cause random problems because the X86 backend is producing mmx stuff without inserting proper emms calls. In the short term, force off MMX datatypes. In the long term, the X86 backend should not select generic vector types to MMX registers. This is being worked on, but won't be done in time for 2.8. rdar://8380055 llvm-svn: 112696
102 lines
3.6 KiB
LLVM
102 lines
3.6 KiB
LLVM
; RUN: opt < %s -scalarrepl -S | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
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define void @test1(<4 x float>* %F, float %f) {
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entry:
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%G = alloca <4 x float>, align 16 ; <<4 x float>*> [#uses=3]
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%tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2]
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%tmp3 = fadd <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp3, <4 x float>* %G
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%G.upgrd.1 = getelementptr <4 x float>* %G, i32 0, i32 0 ; <float*> [#uses=1]
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store float %f, float* %G.upgrd.1
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%tmp4 = load <4 x float>* %G ; <<4 x float>> [#uses=2]
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%tmp6 = fadd <4 x float> %tmp4, %tmp4 ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp6, <4 x float>* %F
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ret void
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; CHECK: @test1
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; CHECK-NOT: alloca
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; CHECK: %tmp = load <4 x float>* %F
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; CHECK: fadd <4 x float> %tmp, %tmp
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; CHECK-NEXT: insertelement <4 x float> %tmp3, float %f, i32 0
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}
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define void @test2(<4 x float>* %F, float %f) {
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entry:
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%G = alloca <4 x float>, align 16 ; <<4 x float>*> [#uses=3]
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%tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2]
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%tmp3 = fadd <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp3, <4 x float>* %G
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%tmp.upgrd.2 = getelementptr <4 x float>* %G, i32 0, i32 2 ; <float*> [#uses=1]
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store float %f, float* %tmp.upgrd.2
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%tmp4 = load <4 x float>* %G ; <<4 x float>> [#uses=2]
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%tmp6 = fadd <4 x float> %tmp4, %tmp4 ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp6, <4 x float>* %F
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ret void
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; CHECK: @test2
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; CHECK-NOT: alloca
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; CHECK: %tmp = load <4 x float>* %F
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; CHECK: fadd <4 x float> %tmp, %tmp
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; CHECK-NEXT: insertelement <4 x float> %tmp3, float %f, i32 2
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}
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define void @test3(<4 x float>* %F, float* %f) {
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entry:
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%G = alloca <4 x float>, align 16 ; <<4 x float>*> [#uses=2]
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%tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2]
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%tmp3 = fadd <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp3, <4 x float>* %G
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%tmp.upgrd.3 = getelementptr <4 x float>* %G, i32 0, i32 2 ; <float*> [#uses=1]
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%tmp.upgrd.4 = load float* %tmp.upgrd.3 ; <float> [#uses=1]
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store float %tmp.upgrd.4, float* %f
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ret void
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; CHECK: @test3
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; CHECK-NOT: alloca
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; CHECK: %tmp = load <4 x float>* %F
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; CHECK: fadd <4 x float> %tmp, %tmp
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; CHECK-NEXT: extractelement <4 x float> %tmp3, i32 2
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}
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define void @test4(<4 x float>* %F, float* %f) {
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entry:
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%G = alloca <4 x float>, align 16 ; <<4 x float>*> [#uses=2]
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%tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2]
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%tmp3 = fadd <4 x float> %tmp, %tmp ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp3, <4 x float>* %G
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%G.upgrd.5 = getelementptr <4 x float>* %G, i32 0, i32 0 ; <float*> [#uses=1]
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%tmp.upgrd.6 = load float* %G.upgrd.5 ; <float> [#uses=1]
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store float %tmp.upgrd.6, float* %f
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ret void
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; CHECK: @test4
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; CHECK-NOT: alloca
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; CHECK: %tmp = load <4 x float>* %F
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; CHECK: fadd <4 x float> %tmp, %tmp
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; CHECK-NEXT: extractelement <4 x float> %tmp3, i32 0
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}
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define i32 @test5(float %X) { ;; should turn into bitcast.
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%X_addr = alloca [4 x float]
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%X1 = getelementptr [4 x float]* %X_addr, i32 0, i32 2
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store float %X, float* %X1
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%a = bitcast float* %X1 to i32*
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%tmp = load i32* %a
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ret i32 %tmp
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; CHECK: @test5
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; CHECK-NEXT: bitcast float %X to i32
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; CHECK-NEXT: ret i32
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}
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;; should not turn into <1 x i64> - It is a banned MMX datatype.
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;; rdar://8380055
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define i64 @test6(<2 x float> %X) {
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%X_addr = alloca <2 x float>
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store <2 x float> %X, <2 x float>* %X_addr
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%P = bitcast <2 x float>* %X_addr to i64*
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%tmp = load i64* %P
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ret i64 %tmp
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; CHECK: @test6
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; CHECK-NEXT: bitcast <2 x float> %X to i64
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; CHECK-NEXT: ret i64
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}
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