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f56e4f6d3d
This re-architects the RISCV relocation handling to bring the implementation closer in line with the implementation in binutils. We would previously aggressively resolve the relocation. With this restructuring, we always will emit a paired relocation for any symbolic difference of the type of S±T[±C] where S and T are labels and C is a constant. GAS has a special target hook controlled by `RELOC_EXPANSION_POSSIBLE` which indicates that a fixup may be expanded into multiple relocations. This is used by the RISCV backend to always emit a paired relocation - either ADD[WIDTH] + SUB[WIDTH] for text relocations or SET[WIDTH] + SUB[WIDTH] for a debug info relocation. Irrespective of whether linker relaxation support is enabled, symbolic difference is always emitted as a paired relocation. This change also sinks the target specific behaviour down into the target specific area rather than exposing it to the shared relocation handling. In the process, we also sink the "special" handling for debug information down into the RISCV target. Although this improves the path for the other targets, this is not necessarily entirely ideal either. The changes in the debug info emission could be done through another type of hook as this functionality would be required by any other target which wishes to do linker relaxation. However, as there are no other targets in LLVM which currently do this, this is a reasonable thing to do until such time as the code needs to be shared. Improve the handling of the relocation (and add a reduced test case from the Linux kernel) to ensure that we handle complex expressions for symbolic difference. This ensures that we correct relocate symbols with the adddends normalized and associated with the addition portion of the paired relocation. This change also addresses some review comments from Alex Bradbury about the relocations meant for use in the DWARF CFA being named incorrectly (using ADD6 instead of SET6) in the original change which introduced the relocation type. This resolves the issues with the symbolic difference emission sufficiently to enable building the Linux kernel with clang+IAS+lld (without linker relaxation). Resolves PR50153, PR50156! Fixes: ClangBuiltLinux/linux#1023, ClangBuiltLinux/linux#1143 Reviewed By: nickdesaulniers, maskray Differential Revision: https://reviews.llvm.org/D103539
46 lines
1.3 KiB
ArmAsm
46 lines
1.3 KiB
ArmAsm
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+relax %s \
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# RUN: | llvm-readobj -r - | FileCheck -check-prefix RELAX %s
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# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=-relax %s \
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# RUN: | llvm-readobj -r - | FileCheck -check-prefix RELAX %s
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# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+relax %s \
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# RUN: | llvm-readobj -r - | FileCheck -check-prefix RELAX %s
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# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=-relax %s \
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# RUN: | llvm-readobj -r - | FileCheck -check-prefix RELAX %s
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# Check that subtraction expressions are emitted as two relocations always.
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.globl G1
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.globl G2
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.L1:
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G1:
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addi a0, a0, 0
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.L2:
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G2:
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.data
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.dword .L2-.L1
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.dword G2-G1
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.word .L2-.L1
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.word G2-G1
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.half .L2-.L1
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.half G2-G1
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.byte .L2-.L1
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.byte G2-G1
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# RELAX: 0x0 R_RISCV_ADD64 .L2 0x0
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# RELAX: 0x0 R_RISCV_SUB64 .L1 0x0
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# RELAX: 0x8 R_RISCV_ADD64 G2 0x0
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# RELAX: 0x8 R_RISCV_SUB64 G1 0x0
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# RELAX: 0x10 R_RISCV_ADD32 .L2 0x0
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# RELAX: 0x10 R_RISCV_SUB32 .L1 0x0
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# RELAX: 0x14 R_RISCV_ADD32 G2 0x0
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# RELAX: 0x14 R_RISCV_SUB32 G1 0x0
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# RELAX: 0x18 R_RISCV_ADD16 .L2 0x0
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# RELAX: 0x18 R_RISCV_SUB16 .L1 0x0
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# RELAX: 0x1A R_RISCV_ADD16 G2 0x0
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# RELAX: 0x1A R_RISCV_SUB16 G1 0x0
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# RELAX: 0x1C R_RISCV_ADD8 .L2 0x0
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# RELAX: 0x1C R_RISCV_SUB8 .L1 0x0
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# RELAX: 0x1D R_RISCV_ADD8 G2 0x0
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# RELAX: 0x1D R_RISCV_SUB8 G1 0x0
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