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218109597e
This makes the llvm-objdump output much more readable and closer to binutils objdump. This builds on D76591 It requires changing the OperandType for certain immediates to "OPERAND_PCREL" so tablegen will generate code to pass the instruction's address. This means we can't do the generic check on these instructions in verifyInstruction any more. Should I add it back with explicit opcode checks? Or should we add a new operand flag to control the passing of address instead of matching the name? Differential Revision: https://reviews.llvm.org/D92147
128 lines
3.2 KiB
ArmAsm
128 lines
3.2 KiB
ArmAsm
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \
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# RUN: | llvm-objdump -d -M no-aliases - | FileCheck --check-prefix=INSTR %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \
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# RUN: | llvm-objdump -d -M no-aliases - | FileCheck --check-prefix=RELAX-INSTR %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \
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# RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELAX-RELOC %s
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FAR_JUMP_NEGATIVE:
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c.nop
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.space 2000
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FAR_BRANCH_NEGATIVE:
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c.nop
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.space 256
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NEAR_NEGATIVE:
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c.nop
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start:
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c.bnez a0, NEAR
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#INSTR: c.bnez a0, 0x91e
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#RELAX-INSTR: c.bnez a0, 0
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#RELAX-RELOC: R_RISCV_RVC_BRANCH
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c.bnez a0, NEAR_NEGATIVE
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#INSTR: c.bnez a0, 0x8d4
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#RELAX-INSTR: c.bnez a0, 0
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#RELAX-RELOC: R_RISCV_RVC_BRANCH
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c.bnez a0, FAR_BRANCH
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#INSTR-NEXT: bne a0, zero, 0xa20
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#RELAX-INSTR-NEXT: bne a0, zero, 0
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#RELAX-RELOC: R_RISCV_BRANCH
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c.bnez a0, FAR_BRANCH_NEGATIVE
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#INSTR-NEXT: bne a0, zero, 0x7d2
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#RELAX-INSTR-NEXT: bne a0, zero, 0
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#RELAX-RELOC: R_RISCV_BRANCH
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c.bnez a0, FAR_JUMP
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#INSTR-NEXT: bne a0, zero, 0x11f2
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#RELAX-INSTR-NEXT: bne a0, zero, 0
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#RELAX-RELOC: R_RISCV_BRANCH
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c.bnez a0, FAR_JUMP_NEGATIVE
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#INSTR-NEXT: bne a0, zero, 0x0
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#RELAX-INSTR-NEXT: bne a0, zero, 0
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#RELAX-RELOC: R_RISCV_BRANCH
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c.beqz a0, NEAR
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#INSTR-NEXT: c.beqz a0, 0x91e
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#RELAX-INSTR-NEXT: c.beqz a0, 0
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#RELAX-RELOC: R_RISCV_RVC_BRANCH
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c.beqz a0, NEAR_NEGATIVE
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#INSTR-NEXT: c.beqz a0, 0x8d4
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#RELAX-INSTR-NEXT: c.beqz a0, 0
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#RELAX-RELOC: R_RISCV_RVC_BRANCH
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c.beqz a0, FAR_BRANCH
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#INSTR-NEXT: beq a0, zero, 0xa20
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#RELAX-INSTR-NEXT: beq a0, zero, 0
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#RELAX-RELOC: R_RISCV_BRANCH
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c.beqz a0, FAR_BRANCH_NEGATIVE
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#INSTR-NEXT: beq a0, zero, 0x7d2
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#RELAX-INSTR-NEXT: beq a0, zero, 0
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#RELAX-RELOC: R_RISCV_BRANCH
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c.beqz a0, FAR_JUMP
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#INSTR-NEXT: beq a0, zero, 0x11f2
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#RELAX-INSTR-NEXT: beq a0, zero, 0
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#RELAX-RELOC: R_RISCV_BRANCH
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c.beqz a0, FAR_JUMP_NEGATIVE
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#INSTR-NEXT: beq a0, zero, 0x0
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#RELAX-INSTR-NEXT: beq a0, zero, 0
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#RELAX-RELOC: R_RISCV_BRANCH
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c.j NEAR
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#INSTR-NEXT: c.j 0x91e
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#RELAX-INSTR-NEXT: c.j 0
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#RELAX-RELOC: R_RISCV_RVC_JUMP
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c.j NEAR_NEGATIVE
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#INSTR-NEXT: c.j 0x8d4
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#RELAX-INSTR-NEXT: c.j 0
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#RELAX-RELOC: R_RISCV_RVC_JUMP
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c.j FAR_BRANCH
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#INSTR-NEXT: c.j 0xa20
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#RELAX-INSTR-NEXT: c.j 0
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#RELAX-RELOC: R_RISCV_RVC_JUMP
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c.j FAR_BRANCH_NEGATIVE
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#INSTR-NEXT: c.j 0x7d2
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#RELAX-INSTR-NEXT: c.j 0
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#RELAX-RELOC: R_RISCV_RVC_JUMP
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c.j FAR_JUMP
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#INSTR-NEXT: jal zero, 0x11f2
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#RELAX-INSTR-NEXT: jal zero, 0
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#RELAX-RELOC: R_RISCV_JAL
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c.j FAR_JUMP_NEGATIVE
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#INSTR-NEXT: jal zero, 0x0
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#RELAX-INSTR-NEXT: jal zero, 0
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#RELAX-RELOC: R_RISCV_JAL
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c.jal NEAR
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#INSTR: c.jal 0x91e
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#RELAX-INSTR: c.jal 0
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#RELAX-RELOC: R_RISCV_RVC_JUMP
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c.jal NEAR_NEGATIVE
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#INSTR: c.jal 0x8d4
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#RELAX-INSTR: c.jal 0
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#RELAX-RELOC: R_RISCV_RVC_JUMP
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c.jal FAR_BRANCH
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#INSTR-NEXT: c.jal 0xa20
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#RELAX-INSTR-NEXT: c.jal 0
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#RELAX-RELOC: R_RISCV_RVC_JUMP
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c.jal FAR_BRANCH_NEGATIVE
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#INSTR-NEXT: c.jal 0x7d2
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#RELAX-INSTR-NEXT: c.jal 0
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#RELAX-RELOC: R_RISCV_RVC_JUMP
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c.jal FAR_JUMP
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#INSTR-NEXT: jal ra, 0x11f2
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#RELAX-INSTR-NEXT: jal ra, 0
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#RELAX-RELOC: R_RISCV_JAL
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c.jal FAR_JUMP_NEGATIVE
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#INSTR-NEXT: jal ra, 0x0
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#RELAX-INSTR-NEXT: jal ra, 0
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#RELAX-RELOC: R_RISCV_JAL
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NEAR:
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c.nop
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.space 256
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FAR_BRANCH:
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c.nop
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.space 2000
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FAR_JUMP:
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c.nop
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