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77f91408dd
Unlike most -- hopefully "all other", but I'm still checking -- memory
instructions we support, LOAD REVERSED and STORE REVERSED may access
the memory location several times. This means that they are not suitable
for volatile loads and stores.
This patch is a prerequisite for better atomic load and store support.
The same principle applies there: almost all memory instructions we
support are inherently atomic ("block concurrent"), but LOAD REVERSED
and STORE REVERSED are exceptions.
Other instructions continue to allow volatile operands. I will add
positive "allows volatile" tests at the same time as the "allows atomic
load or store" tests.
llvm-svn: 183002
100 lines
2.6 KiB
LLVM
100 lines
2.6 KiB
LLVM
; Test 32-bit byteswaps from registers to memory.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare i32 @llvm.bswap.i32(i32 %a)
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; Check STRV with no displacement.
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define void @f1(i32 *%dst, i32 %a) {
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; CHECK: f1:
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; CHECK: strv %r3, 0(%r2)
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; CHECK: br %r14
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%swapped = call i32 @llvm.bswap.i32(i32 %a)
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store i32 %swapped, i32 *%dst
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ret void
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}
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; Check the high end of the aligned STRV range.
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define void @f2(i32 *%dst, i32 %a) {
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; CHECK: f2:
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; CHECK: strv %r3, 524284(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%dst, i64 131071
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%swapped = call i32 @llvm.bswap.i32(i32 %a)
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store i32 %swapped, i32 *%ptr
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ret void
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define void @f3(i32 *%dst, i32 %a) {
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; CHECK: f3:
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; CHECK: agfi %r2, 524288
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; CHECK: strv %r3, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%dst, i64 131072
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%swapped = call i32 @llvm.bswap.i32(i32 %a)
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store i32 %swapped, i32 *%ptr
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ret void
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}
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; Check the high end of the negative aligned STRV range.
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define void @f4(i32 *%dst, i32 %a) {
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; CHECK: f4:
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; CHECK: strv %r3, -4(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%dst, i64 -1
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%swapped = call i32 @llvm.bswap.i32(i32 %a)
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store i32 %swapped, i32 *%ptr
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ret void
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}
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; Check the low end of the STRV range.
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define void @f5(i32 *%dst, i32 %a) {
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; CHECK: f5:
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; CHECK: strv %r3, -524288(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%dst, i64 -131072
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%swapped = call i32 @llvm.bswap.i32(i32 %a)
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store i32 %swapped, i32 *%ptr
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ret void
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define void @f6(i32 *%dst, i32 %a) {
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; CHECK: f6:
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; CHECK: agfi %r2, -524292
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; CHECK: strv %r3, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%dst, i64 -131073
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%swapped = call i32 @llvm.bswap.i32(i32 %a)
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store i32 %swapped, i32 *%ptr
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ret void
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}
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; Check that STRV allows an index.
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define void @f7(i64 %src, i64 %index, i32 %a) {
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; CHECK: f7:
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; CHECK: strv %r4, 524287({{%r3,%r2|%r2,%r3}})
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to i32 *
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%swapped = call i32 @llvm.bswap.i32(i32 %a)
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store i32 %swapped, i32 *%ptr
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ret void
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}
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; Check that volatile stores do not use STRV, which might access the
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; storage multple times.
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define void @f8(i32 *%dst, i32 %a) {
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; CHECK: f8:
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; CHECK: lrvr [[REG:%r[0-5]]], %r3
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; CHECK: st [[REG]], 0(%r2)
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; CHECK: br %r14
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%swapped = call i32 @llvm.bswap.i32(i32 %a)
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store volatile i32 %swapped, i32 *%dst
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ret void
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}
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