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964ffa104f
Add pseudo conditional store instructions, so that we use:
branch foo:
store
foo:
instead of:
load
branch foo:
move
foo:
store
z196 has real 32-bit and 64-bit conditional stores, but we don't use
any z196 instructions yet.
llvm-svn: 185065
215 lines
5.6 KiB
LLVM
215 lines
5.6 KiB
LLVM
; Test 64-bit conditional stores that are presented as selects.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare void @foo(i64 *)
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; Test with the loaded value first.
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define void @f1(i64 *%ptr, i64 %alt, i32 %limit) {
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; CHECK: f1:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: stg %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load i64 *%ptr
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%res = select i1 %cond, i64 %orig, i64 %alt
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store i64 %res, i64 *%ptr
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ret void
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}
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; ...and with the loaded value second
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define void @f2(i64 *%ptr, i64 %alt, i32 %limit) {
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; CHECK: f2:
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; CHECK-NOT: %r2
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; CHECK: jnl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: stg %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load i64 *%ptr
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%res = select i1 %cond, i64 %alt, i64 %orig
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store i64 %res, i64 *%ptr
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ret void
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}
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; Check the high end of the aligned STG range.
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define void @f3(i64 *%base, i64 %alt, i32 %limit) {
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; CHECK: f3:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: stg %r3, 524280(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%ptr = getelementptr i64 *%base, i64 65535
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%cond = icmp ult i32 %limit, 42
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%orig = load i64 *%ptr
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%res = select i1 %cond, i64 %orig, i64 %alt
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store i64 %res, i64 *%ptr
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ret void
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}
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; Check the next doubleword up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define void @f4(i64 *%base, i64 %alt, i32 %limit) {
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; CHECK: f4:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: agfi %r2, 524288
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; CHECK: stg %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%ptr = getelementptr i64 *%base, i64 65536
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%cond = icmp ult i32 %limit, 42
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%orig = load i64 *%ptr
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%res = select i1 %cond, i64 %orig, i64 %alt
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store i64 %res, i64 *%ptr
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ret void
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}
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; Check the low end of the STG range.
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define void @f5(i64 *%base, i64 %alt, i32 %limit) {
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; CHECK: f5:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: stg %r3, -524288(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%ptr = getelementptr i64 *%base, i64 -65536
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%cond = icmp ult i32 %limit, 42
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%orig = load i64 *%ptr
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%res = select i1 %cond, i64 %orig, i64 %alt
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store i64 %res, i64 *%ptr
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ret void
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}
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; Check the next doubleword down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define void @f6(i64 *%base, i64 %alt, i32 %limit) {
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; CHECK: f6:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: agfi %r2, -524296
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; CHECK: stg %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%ptr = getelementptr i64 *%base, i64 -65537
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%cond = icmp ult i32 %limit, 42
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%orig = load i64 *%ptr
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%res = select i1 %cond, i64 %orig, i64 %alt
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store i64 %res, i64 *%ptr
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ret void
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}
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; Check that STG allows an index.
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define void @f7(i64 %base, i64 %index, i64 %alt, i32 %limit) {
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; CHECK: f7:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: stg %r4, 524287(%r3,%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%add1 = add i64 %base, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to i64 *
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%cond = icmp ult i32 %limit, 42
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%orig = load i64 *%ptr
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%res = select i1 %cond, i64 %orig, i64 %alt
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store i64 %res, i64 *%ptr
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ret void
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}
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; Check that volatile loads are not matched.
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define void @f8(i64 *%ptr, i64 %alt, i32 %limit) {
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; CHECK: f8:
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; CHECK: lg {{%r[0-5]}}, 0(%r2)
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; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
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; CHECK: [[LABEL]]:
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; CHECK: stg {{%r[0-5]}}, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load volatile i64 *%ptr
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%res = select i1 %cond, i64 %orig, i64 %alt
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store i64 %res, i64 *%ptr
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ret void
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}
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; ...likewise stores. In this case we should have a conditional load into %r3.
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define void @f9(i64 *%ptr, i64 %alt, i32 %limit) {
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; CHECK: f9:
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; CHECK: jnl [[LABEL:[^ ]*]]
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; CHECK: lg %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: stg %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load i64 *%ptr
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%res = select i1 %cond, i64 %orig, i64 %alt
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store volatile i64 %res, i64 *%ptr
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ret void
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}
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; Check that atomic loads are not matched. The transformation is OK for
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; the "unordered" case tested here, but since we don't try to handle atomic
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; operations at all in this context, it seems better to assert that than
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; to restrict the test to a stronger ordering.
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define void @f10(i64 *%ptr, i64 %alt, i32 %limit) {
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; FIXME: should use a normal load instead of CSG.
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; CHECK: f10:
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; CHECK: csg {{%r[0-5]}}, {{%r[0-5]}}, 0(%r2)
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; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
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; CHECK: [[LABEL]]:
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; CHECK: stg {{%r[0-5]}}, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load atomic i64 *%ptr unordered, align 8
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%res = select i1 %cond, i64 %orig, i64 %alt
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store i64 %res, i64 *%ptr
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ret void
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}
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; ...likewise stores.
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define void @f11(i64 *%ptr, i64 %alt, i32 %limit) {
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; FIXME: should use a normal store instead of CSG.
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; CHECK: f11:
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; CHECK: jnl [[LABEL:[^ ]*]]
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; CHECK: lg %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: csg {{%r[0-5]}}, %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 42
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%orig = load i64 *%ptr
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%res = select i1 %cond, i64 %orig, i64 %alt
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store atomic i64 %res, i64 *%ptr unordered, align 8
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ret void
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}
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; Try a frame index base.
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define void @f12(i64 %alt, i32 %limit) {
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; CHECK: f12:
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; CHECK: brasl %r14, foo@PLT
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; CHECK-NOT: %r15
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r15
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; CHECK: stg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
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; CHECK: [[LABEL]]:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: br %r14
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%ptr = alloca i64
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call void @foo(i64 *%ptr)
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%cond = icmp ult i32 %limit, 42
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%orig = load i64 *%ptr
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%res = select i1 %cond, i64 %orig, i64 %alt
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store i64 %res, i64 *%ptr
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call void @foo(i64 *%ptr)
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ret void
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}
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