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1431b3c2f5
This adds all CodeGen tests for the SystemZ target. This version of the patch incorporates feedback from a review by Sean Silva. Thanks to all reviewers! Patch by Richard Sandiford. llvm-svn: 181204
118 lines
2.7 KiB
LLVM
118 lines
2.7 KiB
LLVM
; Test 32-bit GPR stores.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Test an i32 store.
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define void @f1(i32 *%dst, i32 %val) {
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; CHECK: f1:
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; CHECK: st %r3, 0(%r2)
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; CHECK: br %r14
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store i32 %val, i32 *%dst
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ret void
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}
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; Test a truncating i64 store.
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define void @f2(i32 *%dst, i64 %val) {
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%word = trunc i64 %val to i32
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store i32 %word, i32 *%dst
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ret void
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}
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; Check the high end of the aligned ST range.
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define void @f3(i32 *%dst, i32 %val) {
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; CHECK: f3:
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; CHECK: st %r3, 4092(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%dst, i64 1023
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store i32 %val, i32 *%ptr
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ret void
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}
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; Check the next word up, which should use STY instead of ST.
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define void @f4(i32 *%dst, i32 %val) {
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; CHECK: f4:
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; CHECK: sty %r3, 4096(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%dst, i64 1024
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store i32 %val, i32 *%ptr
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ret void
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}
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; Check the high end of the aligned STY range.
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define void @f5(i32 *%dst, i32 %val) {
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; CHECK: f5:
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; CHECK: sty %r3, 524284(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%dst, i64 131071
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store i32 %val, i32 *%ptr
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ret void
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define void @f6(i32 *%dst, i32 %val) {
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; CHECK: f6:
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; CHECK: agfi %r2, 524288
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; CHECK: st %r3, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%dst, i64 131072
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store i32 %val, i32 *%ptr
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ret void
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}
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; Check the high end of the negative aligned STY range.
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define void @f7(i32 *%dst, i32 %val) {
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; CHECK: f7:
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; CHECK: sty %r3, -4(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%dst, i64 -1
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store i32 %val, i32 *%ptr
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ret void
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}
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; Check the low end of the STY range.
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define void @f8(i32 *%dst, i32 %val) {
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; CHECK: f8:
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; CHECK: sty %r3, -524288(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%dst, i64 -131072
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store i32 %val, i32 *%ptr
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ret void
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define void @f9(i32 *%dst, i32 %val) {
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; CHECK: f9:
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; CHECK: agfi %r2, -524292
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; CHECK: st %r3, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%dst, i64 -131073
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store i32 %val, i32 *%ptr
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ret void
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}
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; Check that ST allows an index.
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define void @f10(i64 %dst, i64 %index, i32 %val) {
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; CHECK: f10:
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; CHECK: st %r4, 4095(%r3,%r2)
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; CHECK: br %r14
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%add1 = add i64 %dst, %index
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%add2 = add i64 %add1, 4095
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%ptr = inttoptr i64 %add2 to i32 *
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store i32 %val, i32 *%ptr
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ret void
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}
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; Check that STY allows an index.
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define void @f11(i64 %dst, i64 %index, i32 %val) {
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; CHECK: f11:
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; CHECK: sty %r4, 4096(%r3,%r2)
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; CHECK: br %r14
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%add1 = add i64 %dst, %index
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%add2 = add i64 %add1, 4096
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%ptr = inttoptr i64 %add2 to i32 *
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store i32 %val, i32 *%ptr
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ret void
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}
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