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ead0e16c6e
This patch does the following: * Fix FIXME on `needsStackRealignment`: it is now shared between multiple targets, implemented in `TargetRegisterInfo`, and isn't `virtual` anymore. This will break out-of-tree targets, silently if they used `virtual` and with a build error if they used `override`. * Factor out `canRealignStack` as a `virtual` function on `TargetRegisterInfo`, by default only looks for the `no-realign-stack` function attribute. Multiple targets duplicated the same `needsStackRealignment` code: - Aarch64. - ARM. - Mips almost: had extra `DEBUG` diagnostic, which the default implementation now has. - PowerPC. - WebAssembly. - x86 almost: has an extra `-force-align-stack` option, which the default implementation now has. The default implementation of `needsStackRealignment` used to just return `false`. My current patch changes the behavior by simply using the above shared behavior. This affects: - AMDGPU - BPF - CppBackend - MSP430 - NVPTX - Sparc - SystemZ - XCore - Out-of-tree targets This is a breaking change! `make check` passes. The only implementation of the `virtual` function (besides the slight different in x86) was Hexagon (which did `MF.getFrameInfo()->getMaxAlignment() > 8`), and potentially some out-of-tree targets. Hexagon now uses the default implementation. `needsStackRealignment` was being overwritten in `<Target>GenRegisterInfo.inc`, to return `false` as the default also did. That was odd and is now gone. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11160 llvm-svn: 242727
192 lines
6.9 KiB
C++
192 lines
6.9 KiB
C++
//===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the base ARM implementation of TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
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#define LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
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#include "MCTargetDesc/ARMBaseInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#define GET_REGINFO_HEADER
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#include "ARMGenRegisterInfo.inc"
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namespace llvm {
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/// Register allocation hints.
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namespace ARMRI {
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enum {
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RegPairOdd = 1,
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RegPairEven = 2
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};
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}
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/// isARMArea1Register - Returns true if the register is a low register (r0-r7)
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/// or a stack/pc register that we should push/pop.
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static inline bool isARMArea1Register(unsigned Reg, bool isIOS) {
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using namespace ARM;
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switch (Reg) {
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case R0: case R1: case R2: case R3:
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case R4: case R5: case R6: case R7:
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case LR: case SP: case PC:
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return true;
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case R8: case R9: case R10: case R11: case R12:
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// For iOS we want r7 and lr to be next to each other.
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return !isIOS;
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default:
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return false;
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}
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}
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static inline bool isARMArea2Register(unsigned Reg, bool isIOS) {
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using namespace ARM;
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switch (Reg) {
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case R8: case R9: case R10: case R11: case R12:
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// iOS has this second area.
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return isIOS;
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default:
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return false;
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}
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}
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static inline bool isARMArea3Register(unsigned Reg, bool isIOS) {
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using namespace ARM;
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switch (Reg) {
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case D15: case D14: case D13: case D12:
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case D11: case D10: case D9: case D8:
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return true;
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default:
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return false;
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}
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}
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static inline bool isCalleeSavedRegister(unsigned Reg,
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const MCPhysReg *CSRegs) {
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for (unsigned i = 0; CSRegs[i]; ++i)
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if (Reg == CSRegs[i])
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return true;
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return false;
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}
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class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
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protected:
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/// BasePtr - ARM physical register used as a base ptr in complex stack
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/// frames. I.e., when we need a 3rd base, not just SP and FP, due to
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/// variable size stack objects.
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unsigned BasePtr;
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// Can be only subclassed.
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explicit ARMBaseRegisterInfo();
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// Return the opcode that implements 'Op', or 0 if no opcode
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unsigned getOpcode(int Op) const;
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public:
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/// Code Generation virtual methods...
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const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
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const uint32_t *getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID) const override;
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const uint32_t *getNoPreservedMask() const;
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/// getThisReturnPreservedMask - Returns a call preserved mask specific to the
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/// case that 'returned' is on an i32 first argument if the calling convention
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/// is one that can (partially) model this attribute with a preserved mask
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/// (i.e. it is a calling convention that uses the same register for the first
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/// i32 argument and an i32 return value)
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///
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/// Should return NULL in the case that the calling convention does not have
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/// this property
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const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
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CallingConv::ID) const;
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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const TargetRegisterClass *
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getPointerRegClass(const MachineFunction &MF,
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unsigned Kind = 0) const override;
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const TargetRegisterClass *
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getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
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const TargetRegisterClass *
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getLargestLegalSuperClass(const TargetRegisterClass *RC,
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const MachineFunction &MF) const override;
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unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const override;
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void getRegAllocationHints(unsigned VirtReg,
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ArrayRef<MCPhysReg> Order,
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SmallVectorImpl<MCPhysReg> &Hints,
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const MachineFunction &MF,
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const VirtRegMap *VRM,
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const LiveRegMatrix *Matrix) const override;
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void updateRegAllocHint(unsigned Reg, unsigned NewReg,
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MachineFunction &MF) const override;
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bool hasBasePointer(const MachineFunction &MF) const;
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bool canRealignStack(const MachineFunction &MF) const override;
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int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
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int Idx) const override;
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bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
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void materializeFrameBaseRegister(MachineBasicBlock *MBB,
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unsigned BaseReg, int FrameIdx,
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int64_t Offset) const override;
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void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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int64_t Offset) const override;
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bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
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int64_t Offset) const override;
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bool cannotEliminateFrame(const MachineFunction &MF) const;
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// Debug information queries.
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unsigned getFrameRegister(const MachineFunction &MF) const override;
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unsigned getBaseRegister() const { return BasePtr; }
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bool isLowRegister(unsigned Reg) const;
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/// emitLoadConstPool - Emits a load from constpool to materialize the
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/// specified immediate.
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virtual void emitLoadConstPool(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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DebugLoc dl, unsigned DestReg, unsigned SubIdx,
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int Val, ARMCC::CondCodes Pred = ARMCC::AL,
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unsigned PredReg = 0,
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unsigned MIFlags = MachineInstr::NoFlags)const;
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/// Code Generation virtual methods...
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bool requiresRegisterScavenging(const MachineFunction &MF) const override;
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bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
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bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
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bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
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void eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS = nullptr) const override;
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/// \brief SrcRC and DstRC will be morphed into NewRC if this returns true
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bool shouldCoalesce(MachineInstr *MI,
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const TargetRegisterClass *SrcRC,
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unsigned SubReg,
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const TargetRegisterClass *DstRC,
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unsigned DstSubReg,
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const TargetRegisterClass *NewRC) const override;
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};
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} // end namespace llvm
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#endif
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