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1adcdc6e96
The VOP3 encoding of these allows any SGPR pair for the i1 output, but this was forced before to always use vcc. This doesn't yet try to use this, but does add the operand to the definitions so the main change is adding vcc to the output of the VOP2 encoding. llvm-svn: 246358
114 lines
3.5 KiB
LLVM
114 lines
3.5 KiB
LLVM
; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s
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; CHECK-LABEL: {{^}}fold_sgpr:
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; CHECK: v_add_i32_e32 v{{[0-9]+}}, vcc, s
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define void @fold_sgpr(i32 addrspace(1)* %out, i32 %fold) {
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entry:
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%tmp0 = icmp ne i32 %fold, 0
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br i1 %tmp0, label %if, label %endif
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if:
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%id = call i32 @llvm.r600.read.tidig.x()
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%offset = add i32 %fold, %id
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%tmp1 = getelementptr i32, i32 addrspace(1)* %out, i32 %offset
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store i32 0, i32 addrspace(1)* %tmp1
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br label %endif
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endif:
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ret void
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}
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; CHECK-LABEL: {{^}}fold_imm:
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; CHECK: v_or_b32_e32 v{{[0-9]+}}, 5
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define void @fold_imm(i32 addrspace(1)* %out, i32 %cmp) {
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entry:
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%fold = add i32 3, 2
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%tmp0 = icmp ne i32 %cmp, 0
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br i1 %tmp0, label %if, label %endif
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if:
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%id = call i32 @llvm.r600.read.tidig.x()
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%val = or i32 %id, %fold
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store i32 %val, i32 addrspace(1)* %out
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br label %endif
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endif:
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ret void
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}
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; CHECK-LABEL: {{^}}fold_64bit_constant_add:
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; CHECK-NOT: s_mov_b64
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; FIXME: It would be better if we could use v_add here and drop the extra
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; v_mov_b32 instructions.
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; CHECK-DAG: s_add_u32 [[LO:s[0-9]+]], s{{[0-9]+}}, 1
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; CHECK-DAG: s_addc_u32 [[HI:s[0-9]+]], s{{[0-9]+}}, 0
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; CHECK-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], [[LO]]
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; CHECK-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], [[HI]]
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; CHECK: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}},
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define void @fold_64bit_constant_add(i64 addrspace(1)* %out, i32 %cmp, i64 %val) {
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entry:
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%tmp0 = add i64 %val, 1
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store i64 %tmp0, i64 addrspace(1)* %out
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ret void
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}
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; Inline constants should always be folded.
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; CHECK-LABEL: {{^}}vector_inline:
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; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}
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; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}
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; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}
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; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}
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define void @vector_inline(<4 x i32> addrspace(1)* %out) {
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entry:
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%tmp0 = call i32 @llvm.r600.read.tidig.x()
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%tmp1 = add i32 %tmp0, 1
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%tmp2 = add i32 %tmp0, 2
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%tmp3 = add i32 %tmp0, 3
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%vec0 = insertelement <4 x i32> undef, i32 %tmp0, i32 0
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%vec1 = insertelement <4 x i32> %vec0, i32 %tmp1, i32 1
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%vec2 = insertelement <4 x i32> %vec1, i32 %tmp2, i32 2
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%vec3 = insertelement <4 x i32> %vec2, i32 %tmp3, i32 3
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%tmp4 = xor <4 x i32> <i32 5, i32 5, i32 5, i32 5>, %vec3
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store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %out
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ret void
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}
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; Immediates with one use should be folded
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; CHECK-LABEL: {{^}}imm_one_use:
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; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 0x64, v{{[0-9]+}}
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define void @imm_one_use(i32 addrspace(1)* %out) {
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entry:
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%tmp0 = call i32 @llvm.r600.read.tidig.x()
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%tmp1 = xor i32 %tmp0, 100
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store i32 %tmp1, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}vector_imm:
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; CHECK: s_movk_i32 [[IMM:s[0-9]+]], 0x64
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; CHECK: v_xor_b32_e32 v{{[0-9]}}, [[IMM]], v{{[0-9]}}
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; CHECK: v_xor_b32_e32 v{{[0-9]}}, [[IMM]], v{{[0-9]}}
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; CHECK: v_xor_b32_e32 v{{[0-9]}}, [[IMM]], v{{[0-9]}}
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; CHECK: v_xor_b32_e32 v{{[0-9]}}, [[IMM]], v{{[0-9]}}
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define void @vector_imm(<4 x i32> addrspace(1)* %out) {
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entry:
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%tmp0 = call i32 @llvm.r600.read.tidig.x()
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%tmp1 = add i32 %tmp0, 1
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%tmp2 = add i32 %tmp0, 2
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%tmp3 = add i32 %tmp0, 3
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%vec0 = insertelement <4 x i32> undef, i32 %tmp0, i32 0
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%vec1 = insertelement <4 x i32> %vec0, i32 %tmp1, i32 1
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%vec2 = insertelement <4 x i32> %vec1, i32 %tmp2, i32 2
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%vec3 = insertelement <4 x i32> %vec2, i32 %tmp3, i32 3
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%tmp4 = xor <4 x i32> <i32 100, i32 100, i32 100, i32 100>, %vec3
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store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.r600.read.tidig.x() #0
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attributes #0 = { readnone }
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