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https://github.com/RPCS3/llvm-mirror.git
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1fa0f655fd
Subtarget feature bits are needed to change instprinter's behavior based on feature bits. Most of the other popular targets were updated back in 2015, in https://reviews.llvm.org/rGb46d0234a6969 we should update it too. Reviewed By: sfertile Differential Revision: https://reviews.llvm.org/D94449
657 lines
22 KiB
C++
657 lines
22 KiB
C++
//===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an PPC MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/PPCInstPrinter.h"
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#include "MCTargetDesc/PPCMCTargetDesc.h"
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#include "MCTargetDesc/PPCPredicates.h"
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#include "PPCInstrInfo.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "asm-printer"
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// FIXME: Once the integrated assembler supports full register names, tie this
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// to the verbose-asm setting.
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static cl::opt<bool>
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FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
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cl::desc("Use full register names when printing assembly"));
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// Useful for testing purposes. Prints vs{31-63} as v{0-31} respectively.
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static cl::opt<bool>
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ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false),
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cl::desc("Prints full register names with vs{31-63} as v{0-31}"));
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// Prints full register names with percent symbol.
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static cl::opt<bool>
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FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden,
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cl::init(false),
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cl::desc("Prints full register names with percent"));
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#define PRINT_ALIAS_INSTR
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#include "PPCGenAsmWriter.inc"
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void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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const char *RegName = getRegisterName(RegNo);
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OS << RegName;
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}
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void PPCInstPrinter::printInst(const MCInst *MI, uint64_t Address,
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StringRef Annot, const MCSubtargetInfo &STI,
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raw_ostream &O) {
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// Customize printing of the addis instruction on AIX. When an operand is a
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// symbol reference, the instruction syntax is changed to look like a load
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// operation, i.e:
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// Transform: addis $rD, $rA, $src --> addis $rD, $src($rA).
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if (TT.isOSAIX() &&
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(MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) &&
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MI->getOperand(2).isExpr()) {
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assert((MI->getOperand(0).isReg() && MI->getOperand(1).isReg()) &&
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"The first and the second operand of an addis instruction"
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" should be registers.");
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assert(isa<MCSymbolRefExpr>(MI->getOperand(2).getExpr()) &&
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"The third operand of an addis instruction should be a symbol "
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"reference expression if it is an expression at all.");
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O << "\taddis ";
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printOperand(MI, 0, STI, O);
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O << ", ";
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printOperand(MI, 2, STI, O);
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O << "(";
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printOperand(MI, 1, STI, O);
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O << ")";
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return;
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}
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// Check if the last operand is an expression with the variant kind
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// VK_PPC_PCREL_OPT. If this is the case then this is a linker optimization
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// relocation and the .reloc directive needs to be added.
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unsigned LastOp = MI->getNumOperands() - 1;
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if (MI->getNumOperands() > 1) {
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const MCOperand &Operand = MI->getOperand(LastOp);
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if (Operand.isExpr()) {
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const MCExpr *Expr = Operand.getExpr();
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const MCSymbolRefExpr *SymExpr =
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static_cast<const MCSymbolRefExpr *>(Expr);
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if (SymExpr && SymExpr->getKind() == MCSymbolRefExpr::VK_PPC_PCREL_OPT) {
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const MCSymbol &Symbol = SymExpr->getSymbol();
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if (MI->getOpcode() == PPC::PLDpc) {
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printInstruction(MI, Address, STI, O);
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O << "\n";
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Symbol.print(O, &MAI);
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O << ":";
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return;
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} else {
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O << "\t.reloc ";
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Symbol.print(O, &MAI);
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O << "-8,R_PPC64_PCREL_OPT,.-(";
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Symbol.print(O, &MAI);
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O << "-8)\n";
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}
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}
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}
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}
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// Check for slwi/srwi mnemonics.
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if (MI->getOpcode() == PPC::RLWINM) {
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unsigned char SH = MI->getOperand(2).getImm();
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unsigned char MB = MI->getOperand(3).getImm();
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unsigned char ME = MI->getOperand(4).getImm();
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bool useSubstituteMnemonic = false;
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if (SH <= 31 && MB == 0 && ME == (31-SH)) {
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O << "\tslwi "; useSubstituteMnemonic = true;
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}
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if (SH <= 31 && MB == (32-SH) && ME == 31) {
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O << "\tsrwi "; useSubstituteMnemonic = true;
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SH = 32-SH;
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}
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if (useSubstituteMnemonic) {
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printOperand(MI, 0, STI, O);
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O << ", ";
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printOperand(MI, 1, STI, O);
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O << ", " << (unsigned int)SH;
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printAnnotation(O, Annot);
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return;
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}
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}
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if (MI->getOpcode() == PPC::RLDICR ||
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MI->getOpcode() == PPC::RLDICR_32) {
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unsigned char SH = MI->getOperand(2).getImm();
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unsigned char ME = MI->getOperand(3).getImm();
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// rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
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if (63-SH == ME) {
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O << "\tsldi ";
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printOperand(MI, 0, STI, O);
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O << ", ";
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printOperand(MI, 1, STI, O);
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O << ", " << (unsigned int)SH;
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printAnnotation(O, Annot);
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return;
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}
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}
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// dcbt[st] is printed manually here because:
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// 1. The assembly syntax is different between embedded and server targets
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// 2. We must print the short mnemonics for TH == 0 because the
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// embedded/server syntax default will not be stable across assemblers
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// The syntax for dcbt is:
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// dcbt ra, rb, th [server]
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// dcbt th, ra, rb [embedded]
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// where th can be omitted when it is 0. dcbtst is the same.
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if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
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unsigned char TH = MI->getOperand(0).getImm();
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O << "\tdcbt";
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if (MI->getOpcode() == PPC::DCBTST)
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O << "st";
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if (TH == 16)
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O << "t";
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O << " ";
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bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE];
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if (IsBookE && TH != 0 && TH != 16)
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O << (unsigned int) TH << ", ";
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printOperand(MI, 1, STI, O);
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O << ", ";
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printOperand(MI, 2, STI, O);
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if (!IsBookE && TH != 0 && TH != 16)
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O << ", " << (unsigned int) TH;
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printAnnotation(O, Annot);
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return;
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}
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if (MI->getOpcode() == PPC::DCBF) {
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unsigned char L = MI->getOperand(0).getImm();
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if (!L || L == 1 || L == 3 || L == 4 || L == 6) {
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O << "\tdcb";
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if (L != 6)
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O << "f";
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if (L == 1)
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O << "l";
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if (L == 3)
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O << "lp";
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if (L == 4)
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O << "ps";
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if (L == 6)
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O << "stps";
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O << " ";
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printOperand(MI, 1, STI, O);
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O << ", ";
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printOperand(MI, 2, STI, O);
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printAnnotation(O, Annot);
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return;
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}
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}
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if (!printAliasInstr(MI, Address, STI, O))
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printInstruction(MI, Address, STI, O);
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printAnnotation(O, Annot);
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}
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void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O,
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const char *Modifier) {
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unsigned Code = MI->getOperand(OpNo).getImm();
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if (StringRef(Modifier) == "cc") {
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switch ((PPC::Predicate)Code) {
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case PPC::PRED_LT_MINUS:
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case PPC::PRED_LT_PLUS:
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case PPC::PRED_LT:
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O << "lt";
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return;
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case PPC::PRED_LE_MINUS:
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case PPC::PRED_LE_PLUS:
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case PPC::PRED_LE:
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O << "le";
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return;
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case PPC::PRED_EQ_MINUS:
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case PPC::PRED_EQ_PLUS:
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case PPC::PRED_EQ:
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O << "eq";
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return;
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case PPC::PRED_GE_MINUS:
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case PPC::PRED_GE_PLUS:
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case PPC::PRED_GE:
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O << "ge";
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return;
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case PPC::PRED_GT_MINUS:
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case PPC::PRED_GT_PLUS:
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case PPC::PRED_GT:
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O << "gt";
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return;
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case PPC::PRED_NE_MINUS:
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case PPC::PRED_NE_PLUS:
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case PPC::PRED_NE:
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O << "ne";
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return;
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case PPC::PRED_UN_MINUS:
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case PPC::PRED_UN_PLUS:
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case PPC::PRED_UN:
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O << "un";
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return;
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case PPC::PRED_NU_MINUS:
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case PPC::PRED_NU_PLUS:
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case PPC::PRED_NU:
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O << "nu";
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return;
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case PPC::PRED_BIT_SET:
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case PPC::PRED_BIT_UNSET:
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llvm_unreachable("Invalid use of bit predicate code");
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}
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llvm_unreachable("Invalid predicate code");
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}
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if (StringRef(Modifier) == "pm") {
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switch ((PPC::Predicate)Code) {
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case PPC::PRED_LT:
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case PPC::PRED_LE:
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case PPC::PRED_EQ:
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case PPC::PRED_GE:
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case PPC::PRED_GT:
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case PPC::PRED_NE:
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case PPC::PRED_UN:
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case PPC::PRED_NU:
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return;
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case PPC::PRED_LT_MINUS:
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case PPC::PRED_LE_MINUS:
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case PPC::PRED_EQ_MINUS:
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case PPC::PRED_GE_MINUS:
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case PPC::PRED_GT_MINUS:
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case PPC::PRED_NE_MINUS:
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case PPC::PRED_UN_MINUS:
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case PPC::PRED_NU_MINUS:
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O << "-";
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return;
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case PPC::PRED_LT_PLUS:
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case PPC::PRED_LE_PLUS:
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case PPC::PRED_EQ_PLUS:
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case PPC::PRED_GE_PLUS:
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case PPC::PRED_GT_PLUS:
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case PPC::PRED_NE_PLUS:
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case PPC::PRED_UN_PLUS:
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case PPC::PRED_NU_PLUS:
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O << "+";
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return;
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case PPC::PRED_BIT_SET:
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case PPC::PRED_BIT_UNSET:
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llvm_unreachable("Invalid use of bit predicate code");
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}
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llvm_unreachable("Invalid predicate code");
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}
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assert(StringRef(Modifier) == "reg" &&
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"Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
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printOperand(MI, OpNo + 1, STI, O);
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}
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void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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unsigned Code = MI->getOperand(OpNo).getImm();
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if (Code == 2)
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O << "-";
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else if (Code == 3)
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O << "+";
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}
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void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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unsigned int Value = MI->getOperand(OpNo).getImm();
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assert(Value <= 1 && "Invalid u1imm argument!");
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O << (unsigned int)Value;
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}
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void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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unsigned int Value = MI->getOperand(OpNo).getImm();
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assert(Value <= 3 && "Invalid u2imm argument!");
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O << (unsigned int)Value;
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}
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void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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unsigned int Value = MI->getOperand(OpNo).getImm();
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assert(Value <= 8 && "Invalid u3imm argument!");
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O << (unsigned int)Value;
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}
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void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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unsigned int Value = MI->getOperand(OpNo).getImm();
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assert(Value <= 15 && "Invalid u4imm argument!");
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O << (unsigned int)Value;
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}
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void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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int Value = MI->getOperand(OpNo).getImm();
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Value = SignExtend32<5>(Value);
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O << (int)Value;
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}
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void PPCInstPrinter::printImmZeroOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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unsigned int Value = MI->getOperand(OpNo).getImm();
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assert(Value == 0 && "Operand must be zero");
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O << (unsigned int)Value;
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}
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void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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unsigned int Value = MI->getOperand(OpNo).getImm();
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assert(Value <= 31 && "Invalid u5imm argument!");
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O << (unsigned int)Value;
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}
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void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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unsigned int Value = MI->getOperand(OpNo).getImm();
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assert(Value <= 63 && "Invalid u6imm argument!");
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O << (unsigned int)Value;
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}
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void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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unsigned int Value = MI->getOperand(OpNo).getImm();
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assert(Value <= 127 && "Invalid u7imm argument!");
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O << (unsigned int)Value;
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}
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// Operands of BUILD_VECTOR are signed and we use this to print operands
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// of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and
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// print as unsigned.
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void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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unsigned char Value = MI->getOperand(OpNo).getImm();
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O << (unsigned int)Value;
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}
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void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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unsigned short Value = MI->getOperand(OpNo).getImm();
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assert(Value <= 1023 && "Invalid u10imm argument!");
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O << (unsigned short)Value;
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}
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void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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unsigned short Value = MI->getOperand(OpNo).getImm();
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assert(Value <= 4095 && "Invalid u12imm argument!");
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O << (unsigned short)Value;
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}
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void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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if (MI->getOperand(OpNo).isImm())
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O << (short)MI->getOperand(OpNo).getImm();
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else
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printOperand(MI, OpNo, STI, O);
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}
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void PPCInstPrinter::printS34ImmOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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if (MI->getOperand(OpNo).isImm()) {
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long long Value = MI->getOperand(OpNo).getImm();
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assert(isInt<34>(Value) && "Invalid s34imm argument!");
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O << (long long)Value;
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}
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else
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printOperand(MI, OpNo, STI, O);
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}
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void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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if (MI->getOperand(OpNo).isImm())
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O << (unsigned short)MI->getOperand(OpNo).getImm();
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else
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printOperand(MI, OpNo, STI, O);
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}
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void PPCInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,
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unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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if (!MI->getOperand(OpNo).isImm())
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return printOperand(MI, OpNo, STI, O);
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int32_t Imm = SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
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if (PrintBranchImmAsAddress) {
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uint64_t Target = Address + Imm;
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if (!TT.isPPC64())
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Target &= 0xffffffff;
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O << formatHex(Target);
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} else {
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// Branches can take an immediate operand. This is used by the branch
|
|
// selection pass to print, for example `.+8` (for ELF) or `$+8` (for AIX)
|
|
// to express an eight byte displacement from the program counter.
|
|
if (!TT.isOSAIX())
|
|
O << ".";
|
|
else
|
|
O << "$";
|
|
|
|
if (Imm >= 0)
|
|
O << "+";
|
|
O << Imm;
|
|
}
|
|
}
|
|
|
|
void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
|
|
const MCSubtargetInfo &STI,
|
|
raw_ostream &O) {
|
|
if (!MI->getOperand(OpNo).isImm())
|
|
return printOperand(MI, OpNo, STI, O);
|
|
|
|
O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
|
|
}
|
|
|
|
void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
|
|
const MCSubtargetInfo &STI, raw_ostream &O) {
|
|
unsigned CCReg = MI->getOperand(OpNo).getReg();
|
|
unsigned RegNo;
|
|
switch (CCReg) {
|
|
default: llvm_unreachable("Unknown CR register");
|
|
case PPC::CR0: RegNo = 0; break;
|
|
case PPC::CR1: RegNo = 1; break;
|
|
case PPC::CR2: RegNo = 2; break;
|
|
case PPC::CR3: RegNo = 3; break;
|
|
case PPC::CR4: RegNo = 4; break;
|
|
case PPC::CR5: RegNo = 5; break;
|
|
case PPC::CR6: RegNo = 6; break;
|
|
case PPC::CR7: RegNo = 7; break;
|
|
}
|
|
O << (0x80 >> RegNo);
|
|
}
|
|
|
|
void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
|
|
const MCSubtargetInfo &STI,
|
|
raw_ostream &O) {
|
|
printS16ImmOperand(MI, OpNo, STI, O);
|
|
O << '(';
|
|
if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
|
|
O << "0";
|
|
else
|
|
printOperand(MI, OpNo + 1, STI, O);
|
|
O << ')';
|
|
}
|
|
|
|
void PPCInstPrinter::printMemRegImm34PCRel(const MCInst *MI, unsigned OpNo,
|
|
const MCSubtargetInfo &STI,
|
|
raw_ostream &O) {
|
|
printS34ImmOperand(MI, OpNo, STI, O);
|
|
O << '(';
|
|
printImmZeroOperand(MI, OpNo + 1, STI, O);
|
|
O << ')';
|
|
}
|
|
|
|
void PPCInstPrinter::printMemRegImm34(const MCInst *MI, unsigned OpNo,
|
|
const MCSubtargetInfo &STI,
|
|
raw_ostream &O) {
|
|
printS34ImmOperand(MI, OpNo, STI, O);
|
|
O << '(';
|
|
printOperand(MI, OpNo + 1, STI, O);
|
|
O << ')';
|
|
}
|
|
|
|
void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
|
|
const MCSubtargetInfo &STI,
|
|
raw_ostream &O) {
|
|
// When used as the base register, r0 reads constant zero rather than
|
|
// the value contained in the register. For this reason, the darwin
|
|
// assembler requires that we print r0 as 0 (no r) when used as the base.
|
|
if (MI->getOperand(OpNo).getReg() == PPC::R0)
|
|
O << "0";
|
|
else
|
|
printOperand(MI, OpNo, STI, O);
|
|
O << ", ";
|
|
printOperand(MI, OpNo + 1, STI, O);
|
|
}
|
|
|
|
void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
|
|
const MCSubtargetInfo &STI, raw_ostream &O) {
|
|
// On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
|
|
// come at the _end_ of the expression.
|
|
const MCOperand &Op = MI->getOperand(OpNo);
|
|
const MCSymbolRefExpr *RefExp = nullptr;
|
|
const MCConstantExpr *ConstExp = nullptr;
|
|
if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Op.getExpr())) {
|
|
RefExp = cast<MCSymbolRefExpr>(BinExpr->getLHS());
|
|
ConstExp = cast<MCConstantExpr>(BinExpr->getRHS());
|
|
} else
|
|
RefExp = cast<MCSymbolRefExpr>(Op.getExpr());
|
|
|
|
O << RefExp->getSymbol().getName();
|
|
// The variant kind VK_PPC_NOTOC needs to be handled as a special case
|
|
// because we do not want the assembly to print out the @notoc at the
|
|
// end like __tls_get_addr(x@tlsgd)@notoc. Instead we want it to look
|
|
// like __tls_get_addr@notoc(x@tlsgd).
|
|
if (RefExp->getKind() == MCSymbolRefExpr::VK_PPC_NOTOC)
|
|
O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind());
|
|
O << '(';
|
|
printOperand(MI, OpNo + 1, STI, O);
|
|
O << ')';
|
|
if (RefExp->getKind() != MCSymbolRefExpr::VK_None &&
|
|
RefExp->getKind() != MCSymbolRefExpr::VK_PPC_NOTOC)
|
|
O << '@' << MCSymbolRefExpr::getVariantKindName(RefExp->getKind());
|
|
if (ConstExp != nullptr)
|
|
O << '+' << ConstExp->getValue();
|
|
}
|
|
|
|
/// showRegistersWithPercentPrefix - Check if this register name should be
|
|
/// printed with a percentage symbol as prefix.
|
|
bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {
|
|
if (!FullRegNamesWithPercent || TT.getOS() == Triple::AIX)
|
|
return false;
|
|
|
|
switch (RegName[0]) {
|
|
default:
|
|
return false;
|
|
case 'r':
|
|
case 'f':
|
|
case 'q':
|
|
case 'v':
|
|
case 'c':
|
|
return true;
|
|
}
|
|
}
|
|
|
|
/// getVerboseConditionalRegName - This method expands the condition register
|
|
/// when requested explicitly or targetting Darwin.
|
|
const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum,
|
|
unsigned RegEncoding)
|
|
const {
|
|
if (!FullRegNames)
|
|
return nullptr;
|
|
if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
|
|
return nullptr;
|
|
const char *CRBits[] = {
|
|
"lt", "gt", "eq", "un",
|
|
"4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un",
|
|
"4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un",
|
|
"4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un",
|
|
"4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",
|
|
"4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un",
|
|
"4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un",
|
|
"4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un"
|
|
};
|
|
return CRBits[RegEncoding];
|
|
}
|
|
|
|
// showRegistersWithPrefix - This method determines whether registers
|
|
// should be number-only or include the prefix.
|
|
bool PPCInstPrinter::showRegistersWithPrefix() const {
|
|
if (TT.getOS() == Triple::AIX)
|
|
return false;
|
|
return FullRegNamesWithPercent || FullRegNames;
|
|
}
|
|
|
|
void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
|
|
const MCSubtargetInfo &STI, raw_ostream &O) {
|
|
const MCOperand &Op = MI->getOperand(OpNo);
|
|
if (Op.isReg()) {
|
|
unsigned Reg = Op.getReg();
|
|
if (!ShowVSRNumsAsVR)
|
|
Reg = PPCInstrInfo::getRegNumForOperand(MII.get(MI->getOpcode()),
|
|
Reg, OpNo);
|
|
|
|
const char *RegName;
|
|
RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg));
|
|
if (RegName == nullptr)
|
|
RegName = getRegisterName(Reg);
|
|
if (showRegistersWithPercentPrefix(RegName))
|
|
O << "%";
|
|
if (!showRegistersWithPrefix())
|
|
RegName = PPCRegisterInfo::stripRegisterPrefix(RegName);
|
|
|
|
O << RegName;
|
|
return;
|
|
}
|
|
|
|
if (Op.isImm()) {
|
|
O << Op.getImm();
|
|
return;
|
|
}
|
|
|
|
assert(Op.isExpr() && "unknown operand kind in printOperand");
|
|
Op.getExpr()->print(O, &MAI);
|
|
}
|