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5c5e25358e
CheckInteger uses an int64_t encoded using a variable width encoding that is optimized for encoding a number with a lot of leading zeros. Negative numbers have no leading zeros so use the largest encoding requiring 9 bytes. I believe its most like we want to check for positive and negative numbers near 0. -1 is quite common due to its use in the 'not' idiom. To optimize for this, we can borrow an idea from the bitcode format and move the sign bit to bit 0 with the magnitude stored in the upper bits. This will drastically increase the number of leading zeros for small magnitudes. Then we can run this value through VBR encoding. This gives a small reduction in the table size on all in tree targets except VE where size increased by about 300 bytes due to intrinsic ids now requiring 3 bytes instead of 2. Since the intrinsic enum space is shared by all targets this an unfortunate consquence of where VE is currently located in the range. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D96317
40 lines
1.3 KiB
TableGen
40 lines
1.3 KiB
TableGen
// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
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include "llvm/Target/Target.td"
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def TestTargetInstrInfo : InstrInfo;
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def TestTarget : Target {
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let InstructionSet = TestTargetInstrInfo;
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}
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let Namespace = "TestNamespace" in {
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def R0 : Register<"r0">;
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foreach i = 0...127 in {
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def GPR#i : RegisterClass<"TestTarget", [i32], 32,
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(add R0)>;
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}
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def GPRAbove127 : RegisterClass<"TestTarget", [i32], 32,
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(add R0)>;
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} // end Namespace TestNamespace
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// CHECK: OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
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// CHECK-NEXT: OPC_RecordChild0, // #0 = $src
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// CHECK-NEXT: OPC_Scope, 14, /*->20*/ // 2 children in Scope
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// CHECK-NEXT: OPC_CheckChild1Integer, 0,
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// CHECK-NEXT: OPC_EmitInteger, MVT::i32, 0|128,1/*128*/,
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// CHECK-NEXT: OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
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// CHECK-NEXT: MVT::i32, 2/*#Ops*/, 1, 0,
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def : Pat<(i32 (add i32:$src, (i32 0))),
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(COPY_TO_REGCLASS GPRAbove127, GPR0:$src)>;
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// CHECK: OPC_CheckChild1Integer, 2,
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// CHECK-NEXT: OPC_EmitInteger, MVT::i32, TestNamespace::GPR127RegClassID,
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// CHECK-NEXT: OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
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// CHECK-NEXT: MVT::i32, 2/*#Ops*/, 1, 0,
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def : Pat<(i32 (add i32:$src, (i32 1))),
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(COPY_TO_REGCLASS GPR127, GPR0:$src)>;
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