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https://github.com/RPCS3/llvm-mirror.git
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0cd5e0dc3b
This seems to have caused incorrect register allocation in some cases, breaking tests in the Zig standard library (PR47278). As discussed on the bug, revert back to green for now. > Record internal state based on register units. This is often more > efficient as there are typically fewer register units to update > compared to iterating over all the aliases of a register. > > Original patch by Matthias Braun, but I've been rebasing and fixing it > for almost 2 years and fixed a few bugs causing intermediate failures > to make this patch independent of the changes in > https://reviews.llvm.org/D52010. This reverts commit 66251f7e1de79a7c1620659b7f58352b8c8e892e, and follow-ups 931a68f26b9a3de853807ffad7b2cd0a2dd30922 and 0671a4c5087d40450603d9d26cf239f1a8b1367e. It also adjust some test expectations.
59 lines
1.9 KiB
LLVM
59 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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define void @bn_mul_comba8(i64* nocapture %r, i64* nocapture readonly %a, i64* nocapture readonly %b) {
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; CHECK-LABEL: bn_mul_comba8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ld 6, 0(4)
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; CHECK-NEXT: ld 7, 0(5)
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; CHECK-NEXT: mulhdu 8, 7, 6
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; CHECK-NEXT: ld 4, 8(4)
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; CHECK-NEXT: mulld 9, 4, 6
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; CHECK-NEXT: mulhdu 4, 4, 6
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; CHECK-NEXT: addc 6, 9, 8
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; CHECK-NEXT: addze 4, 4
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; CHECK-NEXT: ld 5, 8(5)
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; CHECK-NEXT: mulld 8, 5, 7
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; CHECK-NEXT: mulhdu 5, 5, 7
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; CHECK-NEXT: addc 6, 6, 8
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; CHECK-NEXT: addze 5, 5
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; CHECK-NEXT: add 4, 5, 4
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; CHECK-NEXT: cmpld 7, 4, 5
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; CHECK-NEXT: mfocrf 10, 1
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; CHECK-NEXT: rlwinm 10, 10, 29, 31, 31
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; CHECK-NEXT: # implicit-def: $x4
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; CHECK-NEXT: mr 4, 10
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; CHECK-NEXT: clrldi 4, 4, 32
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; CHECK-NEXT: std 4, 0(3)
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; CHECK-NEXT: blr
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%1 = load i64, i64* %a, align 8
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%conv = zext i64 %1 to i128
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%2 = load i64, i64* %b, align 8
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%conv2 = zext i64 %2 to i128
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%mul = mul nuw i128 %conv2, %conv
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%shr = lshr i128 %mul, 64
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%agep = getelementptr inbounds i64, i64* %a, i64 1
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%3 = load i64, i64* %agep, align 8
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%conv14 = zext i64 %3 to i128
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%mul15 = mul nuw i128 %conv14, %conv
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%add17 = add i128 %mul15, %shr
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%shr19 = lshr i128 %add17, 64
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%conv20 = trunc i128 %shr19 to i64
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%bgep = getelementptr inbounds i64, i64* %b, i64 1
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%4 = load i64, i64* %bgep, align 8
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%conv28 = zext i64 %4 to i128
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%mul31 = mul nuw i128 %conv28, %conv2
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%conv32 = and i128 %add17, 18446744073709551615
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%add33 = add i128 %conv32, %mul31
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%shr35 = lshr i128 %add33, 64
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%conv36 = trunc i128 %shr35 to i64
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%add37 = add i64 %conv36, %conv20
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%cmp38 = icmp ult i64 %add37, %conv36
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%conv148 = zext i1 %cmp38 to i64
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store i64 %conv148, i64* %r, align 8
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ret void
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}
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