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65635c700c
From ISA, fcmpu will raise the Floating-Point Invalid Operation Exception (SNaN) if either of the operands is a Signaling NaN by setting the bit VXSNAN. But the instruction description didn't set the mayRaiseFPException which might have impact on the scheduling or some backend optimization. Reviewed By: qiucf Differential Revision: https://reviews.llvm.org/D83937
24 lines
977 B
LLVM
24 lines
977 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s \
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; RUN: -stop-after=finalize-isel -verify-machineinstrs | FileCheck %s
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; Verify if the mayRaiseFPException is set for FCMPD/FCMPS
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define i32 @fcmpu(double %a, double %b) {
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; CHECK-LABEL: name: fcmpu
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; CHECK: bb.0.entry:
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; CHECK: liveins: $f1, $f2
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; CHECK: [[COPY:%[0-9]+]]:f8rc = COPY $f2
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; CHECK: [[COPY1:%[0-9]+]]:f8rc = COPY $f1
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; CHECK: %2:crrc = nofpexcept FCMPUD [[COPY1]], [[COPY]]
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; CHECK: [[COPY2:%[0-9]+]]:crbitrc = COPY %2.sub_gt
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; CHECK: [[LI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = LI8 0
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; CHECK: [[LI8_1:%[0-9]+]]:g8rc_and_g8rc_nox0 = LI8 1
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; CHECK: [[ISEL8_:%[0-9]+]]:g8rc = ISEL8 [[LI8_1]], [[LI8_]], [[COPY2]]
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; CHECK: $x3 = COPY [[ISEL8_]]
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; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3
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entry:
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%r = fcmp ogt double %a, %b
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%g = zext i1 %r to i32
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ret i32 %g
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}
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