mirror of
https://github.com/RPCS3/llvm-mirror.git
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9bcfdf98f1
clear what information these functions are actually using.
This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.
llvm-svn: 92564
454 lines
16 KiB
C++
454 lines
16 KiB
C++
//===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a pattern matching instruction selector for Alpha,
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// converting from a legalized dag to a Alpha dag.
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//
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//===----------------------------------------------------------------------===//
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#include "Alpha.h"
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#include "AlphaTargetMachine.h"
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#include "AlphaISelLowering.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/GlobalValue.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/LLVMContext.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include <algorithm>
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using namespace llvm;
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namespace {
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//===--------------------------------------------------------------------===//
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/// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
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/// instructions for SelectionDAG operations.
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class AlphaDAGToDAGISel : public SelectionDAGISel {
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static const int64_t IMM_LOW = -32768;
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static const int64_t IMM_HIGH = 32767;
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static const int64_t IMM_MULT = 65536;
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static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
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static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW * IMM_MULT;
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static int64_t get_ldah16(int64_t x) {
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int64_t y = x / IMM_MULT;
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if (x % IMM_MULT > IMM_HIGH)
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++y;
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return y;
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}
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static int64_t get_lda16(int64_t x) {
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return x - get_ldah16(x) * IMM_MULT;
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}
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/// get_zapImm - Return a zap mask if X is a valid immediate for a zapnot
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/// instruction (if not, return 0). Note that this code accepts partial
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/// zap masks. For example (and LHS, 1) is a valid zap, as long we know
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/// that the bits 1-7 of LHS are already zero. If LHS is non-null, we are
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/// in checking mode. If LHS is null, we assume that the mask has already
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/// been validated before.
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uint64_t get_zapImm(SDValue LHS, uint64_t Constant) {
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uint64_t BitsToCheck = 0;
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unsigned Result = 0;
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for (unsigned i = 0; i != 8; ++i) {
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if (((Constant >> 8*i) & 0xFF) == 0) {
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// nothing to do.
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} else {
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Result |= 1 << i;
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if (((Constant >> 8*i) & 0xFF) == 0xFF) {
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// If the entire byte is set, zapnot the byte.
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} else if (LHS.getNode() == 0) {
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// Otherwise, if the mask was previously validated, we know its okay
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// to zapnot this entire byte even though all the bits aren't set.
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} else {
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// Otherwise we don't know that the it's okay to zapnot this entire
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// byte. Only do this iff we can prove that the missing bits are
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// already null, so the bytezap doesn't need to really null them.
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BitsToCheck |= ~Constant & (0xFF << 8*i);
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}
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}
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}
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// If there are missing bits in a byte (for example, X & 0xEF00), check to
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// see if the missing bits (0x1000) are already known zero if not, the zap
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// isn't okay to do, as it won't clear all the required bits.
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if (BitsToCheck &&
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!CurDAG->MaskedValueIsZero(LHS,
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APInt(LHS.getValueSizeInBits(),
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BitsToCheck)))
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return 0;
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return Result;
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}
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static uint64_t get_zapImm(uint64_t x) {
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unsigned build = 0;
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for(int i = 0; i != 8; ++i) {
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if ((x & 0x00FF) == 0x00FF)
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build |= 1 << i;
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else if ((x & 0x00FF) != 0)
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return 0;
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x >>= 8;
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}
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return build;
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}
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static uint64_t getNearPower2(uint64_t x) {
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if (!x) return 0;
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unsigned at = CountLeadingZeros_64(x);
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uint64_t complow = 1 << (63 - at);
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uint64_t comphigh = 1 << (64 - at);
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//cerr << x << ":" << complow << ":" << comphigh << "\n";
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if (abs64(complow - x) <= abs64(comphigh - x))
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return complow;
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else
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return comphigh;
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}
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static bool chkRemNearPower2(uint64_t x, uint64_t r, bool swap) {
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uint64_t y = getNearPower2(x);
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if (swap)
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return (y - x) == r;
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else
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return (x - y) == r;
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}
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static bool isFPZ(SDValue N) {
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ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
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return (CN && (CN->getValueAPF().isZero()));
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}
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static bool isFPZn(SDValue N) {
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ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
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return (CN && CN->getValueAPF().isNegZero());
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}
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static bool isFPZp(SDValue N) {
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ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
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return (CN && CN->getValueAPF().isPosZero());
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}
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public:
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explicit AlphaDAGToDAGISel(AlphaTargetMachine &TM)
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: SelectionDAGISel(TM)
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{}
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/// getI64Imm - Return a target constant with the specified value, of type
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/// i64.
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inline SDValue getI64Imm(int64_t Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i64);
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}
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// Select - Convert the specified operand from a target-independent to a
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// target-specific node if it hasn't already been changed.
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SDNode *Select(SDNode *N);
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelect();
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virtual const char *getPassName() const {
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return "Alpha DAG->DAG Pattern Instruction Selection";
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}
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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char ConstraintCode,
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std::vector<SDValue> &OutOps) {
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SDValue Op0;
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switch (ConstraintCode) {
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default: return true;
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case 'm': // memory
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Op0 = Op;
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break;
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}
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OutOps.push_back(Op0);
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return false;
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}
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// Include the pieces autogenerated from the target description.
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#include "AlphaGenDAGISel.inc"
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private:
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/// getTargetMachine - Return a reference to the TargetMachine, casted
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/// to the target-specific type.
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const AlphaTargetMachine &getTargetMachine() {
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return static_cast<const AlphaTargetMachine &>(TM);
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}
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/// getInstrInfo - Return a reference to the TargetInstrInfo, casted
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/// to the target-specific type.
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const AlphaInstrInfo *getInstrInfo() {
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return getTargetMachine().getInstrInfo();
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}
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SDNode *getGlobalBaseReg();
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SDNode *getGlobalRetAddr();
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void SelectCALL(SDNode *Op);
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};
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}
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/// getGlobalBaseReg - Output the instructions required to put the
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/// GOT address into a register.
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///
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SDNode *AlphaDAGToDAGISel::getGlobalBaseReg() {
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unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
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return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
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}
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/// getGlobalRetAddr - Grab the return address.
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///
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SDNode *AlphaDAGToDAGISel::getGlobalRetAddr() {
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unsigned GlobalRetAddr = getInstrInfo()->getGlobalRetAddr(MF);
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return CurDAG->getRegister(GlobalRetAddr, TLI.getPointerTy()).getNode();
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}
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void AlphaDAGToDAGISel::InstructionSelect() {
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// Select target instructions for the DAG.
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SelectRoot(*CurDAG);
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CurDAG->RemoveDeadNodes();
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}
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// Select - Convert the specified operand from a target-independent to a
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// target-specific node if it hasn't already been changed.
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SDNode *AlphaDAGToDAGISel::Select(SDNode *N) {
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if (N->isMachineOpcode()) {
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return NULL; // Already selected.
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}
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DebugLoc dl = N->getDebugLoc();
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switch (N->getOpcode()) {
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default: break;
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case AlphaISD::CALL:
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SelectCALL(N);
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return NULL;
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case ISD::FrameIndex: {
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int FI = cast<FrameIndexSDNode>(N)->getIndex();
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return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
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CurDAG->getTargetFrameIndex(FI, MVT::i32),
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getI64Imm(0));
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}
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case ISD::GLOBAL_OFFSET_TABLE:
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return getGlobalBaseReg();
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case AlphaISD::GlobalRetAddr:
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return getGlobalRetAddr();
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case AlphaISD::DivCall: {
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SDValue Chain = CurDAG->getEntryNode();
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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SDValue N2 = N->getOperand(2);
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Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R24, N1,
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SDValue(0,0));
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Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R25, N2,
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Chain.getValue(1));
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Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, N0,
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Chain.getValue(1));
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SDNode *CNode =
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CurDAG->getMachineNode(Alpha::JSRs, dl, MVT::Other, MVT::Flag,
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Chain, Chain.getValue(1));
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Chain = CurDAG->getCopyFromReg(Chain, dl, Alpha::R27, MVT::i64,
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SDValue(CNode, 1));
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return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain);
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}
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case ISD::READCYCLECOUNTER: {
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SDValue Chain = N->getOperand(0);
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return CurDAG->getMachineNode(Alpha::RPCC, dl, MVT::i64, MVT::Other,
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Chain);
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}
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case ISD::Constant: {
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uint64_t uval = cast<ConstantSDNode>(N)->getZExtValue();
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if (uval == 0) {
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SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
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Alpha::R31, MVT::i64);
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ReplaceUses(SDValue(N, 0), Result);
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return NULL;
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}
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int64_t val = (int64_t)uval;
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int32_t val32 = (int32_t)val;
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if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
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val >= IMM_LOW + IMM_LOW * IMM_MULT)
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break; //(LDAH (LDA))
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if ((uval >> 32) == 0 && //empty upper bits
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val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
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// val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
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break; //(zext (LDAH (LDA)))
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//Else use the constant pool
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ConstantInt *C = ConstantInt::get(
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Type::getInt64Ty(*CurDAG->getContext()), uval);
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SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
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SDNode *Tmp = CurDAG->getMachineNode(Alpha::LDAHr, dl, MVT::i64, CPI,
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SDValue(getGlobalBaseReg(), 0));
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return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
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CPI, SDValue(Tmp, 0), CurDAG->getEntryNode());
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}
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case ISD::TargetConstantFP:
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case ISD::ConstantFP: {
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ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
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bool isDouble = N->getValueType(0) == MVT::f64;
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EVT T = isDouble ? MVT::f64 : MVT::f32;
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if (CN->getValueAPF().isPosZero()) {
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return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
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T, CurDAG->getRegister(Alpha::F31, T),
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CurDAG->getRegister(Alpha::F31, T));
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} else if (CN->getValueAPF().isNegZero()) {
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return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
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T, CurDAG->getRegister(Alpha::F31, T),
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CurDAG->getRegister(Alpha::F31, T));
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} else {
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llvm_report_error("Unhandled FP constant type");
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}
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break;
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}
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case ISD::SETCC:
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if (N->getOperand(0).getNode()->getValueType(0).isFloatingPoint()) {
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ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
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unsigned Opc = Alpha::WTF;
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bool rev = false;
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bool inv = false;
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switch(CC) {
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default: DEBUG(N->dump(CurDAG)); llvm_unreachable("Unknown FP comparison!");
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case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ:
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Opc = Alpha::CMPTEQ; break;
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case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT:
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Opc = Alpha::CMPTLT; break;
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case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE:
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Opc = Alpha::CMPTLE; break;
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case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT:
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Opc = Alpha::CMPTLT; rev = true; break;
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case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE:
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Opc = Alpha::CMPTLE; rev = true; break;
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case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE:
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Opc = Alpha::CMPTEQ; inv = true; break;
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case ISD::SETO:
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Opc = Alpha::CMPTUN; inv = true; break;
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case ISD::SETUO:
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Opc = Alpha::CMPTUN; break;
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};
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SDValue tmp1 = N->getOperand(rev?1:0);
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SDValue tmp2 = N->getOperand(rev?0:1);
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SDNode *cmp = CurDAG->getMachineNode(Opc, dl, MVT::f64, tmp1, tmp2);
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if (inv)
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cmp = CurDAG->getMachineNode(Alpha::CMPTEQ, dl,
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MVT::f64, SDValue(cmp, 0),
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CurDAG->getRegister(Alpha::F31, MVT::f64));
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switch(CC) {
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case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE:
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case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE:
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{
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SDNode* cmp2 = CurDAG->getMachineNode(Alpha::CMPTUN, dl, MVT::f64,
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tmp1, tmp2);
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cmp = CurDAG->getMachineNode(Alpha::ADDT, dl, MVT::f64,
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SDValue(cmp2, 0), SDValue(cmp, 0));
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break;
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}
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default: break;
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}
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SDNode* LD = CurDAG->getMachineNode(Alpha::FTOIT, dl,
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MVT::i64, SDValue(cmp, 0));
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return CurDAG->getMachineNode(Alpha::CMPULT, dl, MVT::i64,
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CurDAG->getRegister(Alpha::R31, MVT::i64),
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SDValue(LD,0));
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}
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break;
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case ISD::AND: {
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ConstantSDNode* SC = NULL;
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ConstantSDNode* MC = NULL;
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if (N->getOperand(0).getOpcode() == ISD::SRL &&
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(MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
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(SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1)))) {
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uint64_t sval = SC->getZExtValue();
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uint64_t mval = MC->getZExtValue();
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// If the result is a zap, let the autogened stuff handle it.
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if (get_zapImm(N->getOperand(0), mval))
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break;
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// given mask X, and shift S, we want to see if there is any zap in the
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// mask if we play around with the botton S bits
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uint64_t dontcare = (~0ULL) >> (64 - sval);
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uint64_t mask = mval << sval;
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if (get_zapImm(mask | dontcare))
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mask = mask | dontcare;
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if (get_zapImm(mask)) {
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SDValue Z =
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SDValue(CurDAG->getMachineNode(Alpha::ZAPNOTi, dl, MVT::i64,
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N->getOperand(0).getOperand(0),
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getI64Imm(get_zapImm(mask))), 0);
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return CurDAG->getMachineNode(Alpha::SRLr, dl, MVT::i64, Z,
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getI64Imm(sval));
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}
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}
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break;
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}
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}
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return SelectCode(N);
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}
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void AlphaDAGToDAGISel::SelectCALL(SDNode *N) {
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//TODO: add flag stuff to prevent nondeturministic breakage!
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SDValue Chain = N->getOperand(0);
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SDValue Addr = N->getOperand(1);
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SDValue InFlag = N->getOperand(N->getNumOperands() - 1);
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DebugLoc dl = N->getDebugLoc();
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if (Addr.getOpcode() == AlphaISD::GPRelLo) {
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SDValue GOT = SDValue(getGlobalBaseReg(), 0);
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Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R29, GOT, InFlag);
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InFlag = Chain.getValue(1);
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Chain = SDValue(CurDAG->getMachineNode(Alpha::BSR, dl, MVT::Other,
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MVT::Flag, Addr.getOperand(0),
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Chain, InFlag), 0);
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} else {
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Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, Addr, InFlag);
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InFlag = Chain.getValue(1);
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Chain = SDValue(CurDAG->getMachineNode(Alpha::JSR, dl, MVT::Other,
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MVT::Flag, Chain, InFlag), 0);
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}
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InFlag = Chain.getValue(1);
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ReplaceUses(SDValue(N, 0), Chain);
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ReplaceUses(SDValue(N, 1), InFlag);
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}
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/// createAlphaISelDag - This pass converts a legalized DAG into a
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/// Alpha-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createAlphaISelDag(AlphaTargetMachine &TM) {
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return new AlphaDAGToDAGISel(TM);
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}
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