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9bcfdf98f1
clear what information these functions are actually using.
This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.
llvm-svn: 92564
822 lines
25 KiB
C++
822 lines
25 KiB
C++
//===-- MSP430ISelDAGToDAG.cpp - A dag to dag inst selector for MSP430 ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the MSP430 target.
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//
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//===----------------------------------------------------------------------===//
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#include "MSP430.h"
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#include "MSP430ISelLowering.h"
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#include "MSP430TargetMachine.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/CallingConv.h"
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#include "llvm/Constants.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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#ifndef NDEBUG
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static cl::opt<bool>
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ViewRMWDAGs("view-msp430-rmw-dags", cl::Hidden,
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cl::desc("Pop up a window to show isel dags after RMW preprocess"));
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#else
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static const bool ViewRMWDAGs = false;
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#endif
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STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
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namespace {
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struct MSP430ISelAddressMode {
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enum {
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RegBase,
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FrameIndexBase
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} BaseType;
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struct { // This is really a union, discriminated by BaseType!
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SDValue Reg;
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int FrameIndex;
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} Base;
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int16_t Disp;
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GlobalValue *GV;
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Constant *CP;
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BlockAddress *BlockAddr;
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const char *ES;
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int JT;
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unsigned Align; // CP alignment.
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MSP430ISelAddressMode()
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: BaseType(RegBase), Disp(0), GV(0), CP(0), BlockAddr(0),
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ES(0), JT(-1), Align(0) {
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}
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bool hasSymbolicDisplacement() const {
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return GV != 0 || CP != 0 || ES != 0 || JT != -1;
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}
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bool hasBaseReg() const {
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return Base.Reg.getNode() != 0;
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}
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void setBaseReg(SDValue Reg) {
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BaseType = RegBase;
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Base.Reg = Reg;
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}
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void dump() {
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errs() << "MSP430ISelAddressMode " << this << '\n';
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if (BaseType == RegBase && Base.Reg.getNode() != 0) {
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errs() << "Base.Reg ";
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Base.Reg.getNode()->dump();
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} else if (BaseType == FrameIndexBase) {
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errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
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}
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errs() << " Disp " << Disp << '\n';
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if (GV) {
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errs() << "GV ";
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GV->dump();
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} else if (CP) {
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errs() << " CP ";
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CP->dump();
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errs() << " Align" << Align << '\n';
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} else if (ES) {
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errs() << "ES ";
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errs() << ES << '\n';
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} else if (JT != -1)
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errs() << " JT" << JT << " Align" << Align << '\n';
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}
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};
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}
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/// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine
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/// instructions for SelectionDAG operations.
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///
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namespace {
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class MSP430DAGToDAGISel : public SelectionDAGISel {
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MSP430TargetLowering &Lowering;
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const MSP430Subtarget &Subtarget;
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public:
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MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel)
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: SelectionDAGISel(TM, OptLevel),
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Lowering(*TM.getTargetLowering()),
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Subtarget(*TM.getSubtargetImpl()) { }
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virtual void InstructionSelect();
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virtual const char *getPassName() const {
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return "MSP430 DAG->DAG Pattern Instruction Selection";
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}
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bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
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bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
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bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
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bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
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SDNode *Root) const;
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virtual bool
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SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
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std::vector<SDValue> &OutOps);
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// Include the pieces autogenerated from the target description.
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#include "MSP430GenDAGISel.inc"
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private:
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DenseMap<SDNode*, SDNode*> RMWStores;
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void PreprocessForRMW();
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SDNode *Select(SDNode *N);
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SDNode *SelectIndexedLoad(SDNode *Op);
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SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
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unsigned Opc8, unsigned Opc16);
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bool SelectAddr(SDNode *Op, SDValue Addr, SDValue &Base, SDValue &Disp);
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#ifndef NDEBUG
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unsigned Indent;
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#endif
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};
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} // end anonymous namespace
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/// createMSP430ISelDag - This pass converts a legalized DAG into a
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/// MSP430-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM,
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CodeGenOpt::Level OptLevel) {
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return new MSP430DAGToDAGISel(TM, OptLevel);
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}
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/// MatchWrapper - Try to match MSP430ISD::Wrapper node into an addressing mode.
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/// These wrap things that will resolve down into a symbol reference. If no
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/// match is possible, this returns true, otherwise it returns false.
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bool MSP430DAGToDAGISel::MatchWrapper(SDValue N, MSP430ISelAddressMode &AM) {
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// If the addressing mode already has a symbol as the displacement, we can
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// never match another symbol.
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if (AM.hasSymbolicDisplacement())
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return true;
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SDValue N0 = N.getOperand(0);
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
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AM.GV = G->getGlobal();
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AM.Disp += G->getOffset();
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//AM.SymbolFlags = G->getTargetFlags();
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} else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
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AM.CP = CP->getConstVal();
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AM.Align = CP->getAlignment();
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AM.Disp += CP->getOffset();
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//AM.SymbolFlags = CP->getTargetFlags();
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} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
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AM.ES = S->getSymbol();
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//AM.SymbolFlags = S->getTargetFlags();
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} else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
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AM.JT = J->getIndex();
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//AM.SymbolFlags = J->getTargetFlags();
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} else {
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AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
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//AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
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}
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return false;
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}
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/// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
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/// specified addressing mode without any further recursion.
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bool MSP430DAGToDAGISel::MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM) {
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// Is the base register already occupied?
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if (AM.BaseType != MSP430ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
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// If so, we cannot select it.
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return true;
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}
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// Default, generate it as a register.
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AM.BaseType = MSP430ISelAddressMode::RegBase;
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AM.Base.Reg = N;
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return false;
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}
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bool MSP430DAGToDAGISel::MatchAddress(SDValue N, MSP430ISelAddressMode &AM) {
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DEBUG({
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errs() << "MatchAddress: ";
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AM.dump();
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});
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switch (N.getOpcode()) {
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default: break;
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case ISD::Constant: {
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uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
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AM.Disp += Val;
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return false;
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}
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case MSP430ISD::Wrapper:
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if (!MatchWrapper(N, AM))
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return false;
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break;
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case ISD::FrameIndex:
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if (AM.BaseType == MSP430ISelAddressMode::RegBase
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&& AM.Base.Reg.getNode() == 0) {
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AM.BaseType = MSP430ISelAddressMode::FrameIndexBase;
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AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
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return false;
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}
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break;
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case ISD::ADD: {
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MSP430ISelAddressMode Backup = AM;
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if (!MatchAddress(N.getNode()->getOperand(0), AM) &&
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!MatchAddress(N.getNode()->getOperand(1), AM))
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return false;
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AM = Backup;
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if (!MatchAddress(N.getNode()->getOperand(1), AM) &&
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!MatchAddress(N.getNode()->getOperand(0), AM))
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return false;
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AM = Backup;
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break;
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}
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case ISD::OR:
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// Handle "X | C" as "X + C" iff X is known to have C bits clear.
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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MSP430ISelAddressMode Backup = AM;
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uint64_t Offset = CN->getSExtValue();
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// Start with the LHS as an addr mode.
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if (!MatchAddress(N.getOperand(0), AM) &&
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// Address could not have picked a GV address for the displacement.
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AM.GV == NULL &&
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// Check to see if the LHS & C is zero.
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CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
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AM.Disp += Offset;
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return false;
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}
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AM = Backup;
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}
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break;
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}
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return MatchAddressBase(N, AM);
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}
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/// SelectAddr - returns true if it is able pattern match an addressing mode.
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/// It returns the operands which make up the maximal addressing mode it can
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/// match by reference.
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bool MSP430DAGToDAGISel::SelectAddr(SDNode *Op, SDValue N,
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SDValue &Base, SDValue &Disp) {
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MSP430ISelAddressMode AM;
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if (MatchAddress(N, AM))
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return false;
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EVT VT = N.getValueType();
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if (AM.BaseType == MSP430ISelAddressMode::RegBase) {
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if (!AM.Base.Reg.getNode())
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AM.Base.Reg = CurDAG->getRegister(0, VT);
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}
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Base = (AM.BaseType == MSP430ISelAddressMode::FrameIndexBase) ?
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CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
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AM.Base.Reg;
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if (AM.GV)
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Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i16, AM.Disp,
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0/*AM.SymbolFlags*/);
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else if (AM.CP)
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Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16,
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AM.Align, AM.Disp, 0/*AM.SymbolFlags*/);
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else if (AM.ES)
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Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i16, 0/*AM.SymbolFlags*/);
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else if (AM.JT != -1)
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Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i16, 0/*AM.SymbolFlags*/);
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else if (AM.BlockAddr)
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Disp = CurDAG->getBlockAddress(AM.BlockAddr, MVT::i32,
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true, 0/*AM.SymbolFlags*/);
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else
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Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i16);
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return true;
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}
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bool MSP430DAGToDAGISel::
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SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
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std::vector<SDValue> &OutOps) {
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SDValue Op0, Op1;
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switch (ConstraintCode) {
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default: return true;
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case 'm': // memory
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if (!SelectAddr(Op.getNode(), Op, Op0, Op1))
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return true;
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break;
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}
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OutOps.push_back(Op0);
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OutOps.push_back(Op1);
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return false;
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}
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bool MSP430DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
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SDNode *Root) const {
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if (OptLevel == CodeGenOpt::None) return false;
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/// RMW preprocessing creates the following code:
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/// [Load1]
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/// ^ ^
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/// / |
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/// / |
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/// [Load2] |
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/// ^ ^ |
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/// | | |
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/// | \-|
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/// | |
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/// | [Op]
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/// | ^
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/// | |
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/// \ /
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/// \ /
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/// [Store]
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///
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/// The path Store => Load2 => Load1 is via chain. Note that in general it is
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/// not allowed to fold Load1 into Op (and Store) since it will creates a
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/// cycle. However, this is perfectly legal for the loads moved below the
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/// TokenFactor by PreprocessForRMW. Query the map Store => Load1 (created
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/// during preprocessing) to determine whether it's legal to introduce such
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/// "cycle" for a moment.
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DenseMap<SDNode*, SDNode*>::const_iterator I = RMWStores.find(Root);
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if (I != RMWStores.end() && I->second == N)
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return true;
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// Proceed to 'generic' cycle finder code
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return SelectionDAGISel::IsLegalAndProfitableToFold(N, U, Root);
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}
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/// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
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/// and move load below the TokenFactor. Replace store's chain operand with
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/// load's chain result.
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static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
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SDValue Store, SDValue TF) {
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SmallVector<SDValue, 4> Ops;
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for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; ++i)
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if (Load.getNode() == TF.getOperand(i).getNode())
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Ops.push_back(Load.getOperand(0));
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else
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Ops.push_back(TF.getOperand(i));
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SDValue NewTF = CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size());
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SDValue NewLoad = CurDAG->UpdateNodeOperands(Load, NewTF,
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Load.getOperand(1),
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Load.getOperand(2));
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CurDAG->UpdateNodeOperands(Store, NewLoad.getValue(1), Store.getOperand(1),
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Store.getOperand(2), Store.getOperand(3));
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}
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/// MoveBelowTokenFactor2 - Replace TokenFactor operand with load's chain operand
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/// and move load below the TokenFactor. Replace store's chain operand with
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/// load's chain result. This a version which sinks two loads below token factor.
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/// Look into PreprocessForRMW comments for explanation of transform.
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static void MoveBelowTokenFactor2(SelectionDAG *CurDAG,
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SDValue Load1, SDValue Load2,
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SDValue Store, SDValue TF) {
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SmallVector<SDValue, 4> Ops;
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for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; ++i) {
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SDNode* N = TF.getOperand(i).getNode();
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if (Load2.getNode() == N)
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Ops.push_back(Load2.getOperand(0));
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else if (Load1.getNode() != N)
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Ops.push_back(TF.getOperand(i));
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}
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SDValue NewTF = SDValue(CurDAG->MorphNodeTo(TF.getNode(),
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TF.getOpcode(),
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TF.getNode()->getVTList(),
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&Ops[0], Ops.size()), TF.getResNo());
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SDValue NewLoad2 = CurDAG->UpdateNodeOperands(Load2, NewTF,
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Load2.getOperand(1),
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Load2.getOperand(2));
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SDValue NewLoad1 = CurDAG->UpdateNodeOperands(Load1, NewLoad2.getValue(1),
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Load1.getOperand(1),
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Load1.getOperand(2));
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CurDAG->UpdateNodeOperands(Store,
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NewLoad1.getValue(1),
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Store.getOperand(1),
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Store.getOperand(2), Store.getOperand(3));
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}
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/// isAllowedToSink - return true if N a load which can be moved below token
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/// factor. Basically, the load should be non-volatile and has single use.
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static bool isLoadAllowedToSink(SDValue N, SDValue Chain) {
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if (N.getOpcode() == ISD::BIT_CONVERT)
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N = N.getOperand(0);
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LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
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if (!LD || LD->isVolatile())
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return false;
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if (LD->getAddressingMode() != ISD::UNINDEXED)
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return false;
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ISD::LoadExtType ExtType = LD->getExtensionType();
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if (ExtType != ISD::NON_EXTLOAD && ExtType != ISD::EXTLOAD)
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return false;
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return (N.hasOneUse() &&
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LD->hasNUsesOfValue(1, 1) &&
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LD->isOperandOf(Chain.getNode()));
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}
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/// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG.
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/// The chain produced by the load must only be used by the store's chain
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/// operand, otherwise this may produce a cycle in the DAG.
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static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address,
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SDValue &Load) {
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if (isLoadAllowedToSink(N, Chain) &&
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N.getOperand(1) == Address) {
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Load = N;
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return true;
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}
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return false;
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}
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/// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
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/// This is only run if not in -O0 mode.
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/// This allows the instruction selector to pick more read-modify-write
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/// instructions. This is a common case:
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///
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/// [Load chain]
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/// ^
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/// |
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/// [Load]
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/// ^ ^
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/// | |
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/// / \-
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/// / |
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/// [TokenFactor] [Op]
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/// ^ ^
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/// | |
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/// \ /
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/// \ /
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/// [Store]
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///
|
|
/// The fact the store's chain operand != load's chain will prevent the
|
|
/// (store (op (load))) instruction from being selected. We can transform it to:
|
|
///
|
|
/// [Load chain]
|
|
/// ^
|
|
/// |
|
|
/// [TokenFactor]
|
|
/// ^
|
|
/// |
|
|
/// [Load]
|
|
/// ^ ^
|
|
/// | |
|
|
/// | \-
|
|
/// | |
|
|
/// | [Op]
|
|
/// | ^
|
|
/// | |
|
|
/// \ /
|
|
/// \ /
|
|
/// [Store]
|
|
///
|
|
/// We also recognize the case where second operand of Op is load as well and
|
|
/// move it below token factor as well creating DAG as follows:
|
|
///
|
|
/// [Load chain]
|
|
/// ^
|
|
/// |
|
|
/// [TokenFactor]
|
|
/// ^
|
|
/// |
|
|
/// [Load1]
|
|
/// ^ ^
|
|
/// / |
|
|
/// / |
|
|
/// [Load2] |
|
|
/// ^ ^ |
|
|
/// | | |
|
|
/// | \-|
|
|
/// | |
|
|
/// | [Op]
|
|
/// | ^
|
|
/// | |
|
|
/// \ /
|
|
/// \ /
|
|
/// [Store]
|
|
///
|
|
/// This allows selection of mem-mem instructions. Yay!
|
|
|
|
void MSP430DAGToDAGISel::PreprocessForRMW() {
|
|
for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
|
|
E = CurDAG->allnodes_end(); I != E; ++I) {
|
|
if (!ISD::isNON_TRUNCStore(I))
|
|
continue;
|
|
SDValue Chain = I->getOperand(0);
|
|
|
|
if (Chain.getNode()->getOpcode() != ISD::TokenFactor)
|
|
continue;
|
|
|
|
SDValue N1 = I->getOperand(1);
|
|
SDValue N2 = I->getOperand(2);
|
|
if ((N1.getValueType().isFloatingPoint() &&
|
|
!N1.getValueType().isVector()) ||
|
|
!N1.hasOneUse())
|
|
continue;
|
|
|
|
unsigned RModW = 0;
|
|
SDValue Load1, Load2;
|
|
unsigned Opcode = N1.getNode()->getOpcode();
|
|
switch (Opcode) {
|
|
case ISD::ADD:
|
|
case ISD::AND:
|
|
case ISD::OR:
|
|
case ISD::XOR:
|
|
case ISD::ADDC:
|
|
case ISD::ADDE: {
|
|
SDValue N10 = N1.getOperand(0);
|
|
SDValue N11 = N1.getOperand(1);
|
|
if (isRMWLoad(N10, Chain, N2, Load1)) {
|
|
if (isLoadAllowedToSink(N11, Chain)) {
|
|
Load2 = N11;
|
|
RModW = 2;
|
|
} else
|
|
RModW = 1;
|
|
} else if (isRMWLoad(N11, Chain, N2, Load1)) {
|
|
if (isLoadAllowedToSink(N10, Chain)) {
|
|
Load2 = N10;
|
|
RModW = 2;
|
|
} else
|
|
RModW = 1;
|
|
}
|
|
break;
|
|
}
|
|
case ISD::SUB:
|
|
case ISD::SUBC:
|
|
case ISD::SUBE: {
|
|
SDValue N10 = N1.getOperand(0);
|
|
SDValue N11 = N1.getOperand(1);
|
|
if (isRMWLoad(N10, Chain, N2, Load1)) {
|
|
if (isLoadAllowedToSink(N11, Chain)) {
|
|
Load2 = N11;
|
|
RModW = 2;
|
|
} else
|
|
RModW = 1;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
NumLoadMoved += RModW;
|
|
if (RModW == 1)
|
|
MoveBelowTokenFactor(CurDAG, Load1, SDValue(I, 0), Chain);
|
|
else if (RModW == 2) {
|
|
MoveBelowTokenFactor2(CurDAG, Load1, Load2, SDValue(I, 0), Chain);
|
|
SDNode* Store = I;
|
|
RMWStores[Store] = Load2.getNode();
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
static bool isValidIndexedLoad(const LoadSDNode *LD) {
|
|
ISD::MemIndexedMode AM = LD->getAddressingMode();
|
|
if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD)
|
|
return false;
|
|
|
|
EVT VT = LD->getMemoryVT();
|
|
|
|
switch (VT.getSimpleVT().SimpleTy) {
|
|
case MVT::i8:
|
|
// Sanity check
|
|
if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 1)
|
|
return false;
|
|
|
|
break;
|
|
case MVT::i16:
|
|
// Sanity check
|
|
if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 2)
|
|
return false;
|
|
|
|
break;
|
|
default:
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
SDNode *MSP430DAGToDAGISel::SelectIndexedLoad(SDNode *N) {
|
|
LoadSDNode *LD = cast<LoadSDNode>(N);
|
|
if (!isValidIndexedLoad(LD))
|
|
return NULL;
|
|
|
|
MVT VT = LD->getMemoryVT().getSimpleVT();
|
|
|
|
unsigned Opcode = 0;
|
|
switch (VT.SimpleTy) {
|
|
case MVT::i8:
|
|
Opcode = MSP430::MOV8rm_POST;
|
|
break;
|
|
case MVT::i16:
|
|
Opcode = MSP430::MOV16rm_POST;
|
|
break;
|
|
default:
|
|
return NULL;
|
|
}
|
|
|
|
return CurDAG->getMachineNode(Opcode, N->getDebugLoc(),
|
|
VT, MVT::i16, MVT::Other,
|
|
LD->getBasePtr(), LD->getChain());
|
|
}
|
|
|
|
SDNode *MSP430DAGToDAGISel::SelectIndexedBinOp(SDNode *Op,
|
|
SDValue N1, SDValue N2,
|
|
unsigned Opc8, unsigned Opc16) {
|
|
if (N1.getOpcode() == ISD::LOAD &&
|
|
N1.hasOneUse() &&
|
|
IsLegalAndProfitableToFold(N1.getNode(), Op, Op)) {
|
|
LoadSDNode *LD = cast<LoadSDNode>(N1);
|
|
if (!isValidIndexedLoad(LD))
|
|
return NULL;
|
|
|
|
MVT VT = LD->getMemoryVT().getSimpleVT();
|
|
unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
|
|
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
|
|
MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
|
|
SDValue Ops0[] = { N2, LD->getBasePtr(), LD->getChain() };
|
|
SDNode *ResNode =
|
|
CurDAG->SelectNodeTo(Op, Opc,
|
|
VT, MVT::i16, MVT::Other,
|
|
Ops0, 3);
|
|
cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
|
|
// Transfer chain.
|
|
ReplaceUses(SDValue(N1.getNode(), 2), SDValue(ResNode, 2));
|
|
// Transfer writeback.
|
|
ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
|
|
return ResNode;
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
|
|
/// InstructionSelect - This callback is invoked by
|
|
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
|
|
void MSP430DAGToDAGISel::InstructionSelect() {
|
|
std::string BlockName;
|
|
if (ViewRMWDAGs)
|
|
BlockName = MF->getFunction()->getNameStr() + ":" +
|
|
BB->getBasicBlock()->getNameStr();
|
|
|
|
PreprocessForRMW();
|
|
|
|
if (ViewRMWDAGs) CurDAG->viewGraph("RMW preprocessed:" + BlockName);
|
|
|
|
DEBUG(errs() << "Selection DAG after RMW preprocessing:\n");
|
|
DEBUG(CurDAG->dump());
|
|
|
|
// Codegen the basic block.
|
|
DEBUG(errs() << "===== Instruction selection begins:\n");
|
|
DEBUG(Indent = 0);
|
|
SelectRoot(*CurDAG);
|
|
DEBUG(errs() << "===== Instruction selection ends:\n");
|
|
|
|
CurDAG->RemoveDeadNodes();
|
|
RMWStores.clear();
|
|
}
|
|
|
|
SDNode *MSP430DAGToDAGISel::Select(SDNode *Node) {
|
|
DebugLoc dl = Node->getDebugLoc();
|
|
|
|
// Dump information about the Node being selected
|
|
DEBUG(errs().indent(Indent) << "Selecting: ");
|
|
DEBUG(Node->dump(CurDAG));
|
|
DEBUG(errs() << "\n");
|
|
DEBUG(Indent += 2);
|
|
|
|
// If we have a custom node, we already have selected!
|
|
if (Node->isMachineOpcode()) {
|
|
DEBUG(errs().indent(Indent-2) << "== ";
|
|
Node->dump(CurDAG);
|
|
errs() << "\n");
|
|
DEBUG(Indent -= 2);
|
|
return NULL;
|
|
}
|
|
|
|
// Few custom selection stuff.
|
|
switch (Node->getOpcode()) {
|
|
default: break;
|
|
case ISD::FrameIndex: {
|
|
assert(Node->getValueType(0) == MVT::i16);
|
|
int FI = cast<FrameIndexSDNode>(Node)->getIndex();
|
|
SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16);
|
|
if (Node->hasOneUse())
|
|
return CurDAG->SelectNodeTo(Node, MSP430::ADD16ri, MVT::i16,
|
|
TFI, CurDAG->getTargetConstant(0, MVT::i16));
|
|
return CurDAG->getMachineNode(MSP430::ADD16ri, dl, MVT::i16,
|
|
TFI, CurDAG->getTargetConstant(0, MVT::i16));
|
|
}
|
|
case ISD::LOAD:
|
|
if (SDNode *ResNode = SelectIndexedLoad(Node))
|
|
return ResNode;
|
|
// Other cases are autogenerated.
|
|
break;
|
|
case ISD::ADD:
|
|
if (SDNode *ResNode =
|
|
SelectIndexedBinOp(Node,
|
|
Node->getOperand(0), Node->getOperand(1),
|
|
MSP430::ADD8rm_POST, MSP430::ADD16rm_POST))
|
|
return ResNode;
|
|
else if (SDNode *ResNode =
|
|
SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
|
|
MSP430::ADD8rm_POST, MSP430::ADD16rm_POST))
|
|
return ResNode;
|
|
|
|
// Other cases are autogenerated.
|
|
break;
|
|
case ISD::SUB:
|
|
if (SDNode *ResNode =
|
|
SelectIndexedBinOp(Node,
|
|
Node->getOperand(0), Node->getOperand(1),
|
|
MSP430::SUB8rm_POST, MSP430::SUB16rm_POST))
|
|
return ResNode;
|
|
|
|
// Other cases are autogenerated.
|
|
break;
|
|
case ISD::AND:
|
|
if (SDNode *ResNode =
|
|
SelectIndexedBinOp(Node,
|
|
Node->getOperand(0), Node->getOperand(1),
|
|
MSP430::AND8rm_POST, MSP430::AND16rm_POST))
|
|
return ResNode;
|
|
else if (SDNode *ResNode =
|
|
SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
|
|
MSP430::AND8rm_POST, MSP430::AND16rm_POST))
|
|
return ResNode;
|
|
|
|
// Other cases are autogenerated.
|
|
break;
|
|
case ISD::OR:
|
|
if (SDNode *ResNode =
|
|
SelectIndexedBinOp(Node,
|
|
Node->getOperand(0), Node->getOperand(1),
|
|
MSP430::OR8rm_POST, MSP430::OR16rm_POST))
|
|
return ResNode;
|
|
else if (SDNode *ResNode =
|
|
SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
|
|
MSP430::OR8rm_POST, MSP430::OR16rm_POST))
|
|
return ResNode;
|
|
|
|
// Other cases are autogenerated.
|
|
break;
|
|
case ISD::XOR:
|
|
if (SDNode *ResNode =
|
|
SelectIndexedBinOp(Node,
|
|
Node->getOperand(0), Node->getOperand(1),
|
|
MSP430::XOR8rm_POST, MSP430::XOR16rm_POST))
|
|
return ResNode;
|
|
else if (SDNode *ResNode =
|
|
SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
|
|
MSP430::XOR8rm_POST, MSP430::XOR16rm_POST))
|
|
return ResNode;
|
|
|
|
// Other cases are autogenerated.
|
|
break;
|
|
}
|
|
|
|
// Select the default instruction
|
|
SDNode *ResNode = SelectCode(Node);
|
|
|
|
DEBUG(errs() << std::string(Indent-2, ' ') << "=> ");
|
|
if (ResNode == NULL || ResNode == Node)
|
|
DEBUG(Node->dump(CurDAG));
|
|
else
|
|
DEBUG(ResNode->dump(CurDAG));
|
|
DEBUG(errs() << "\n");
|
|
DEBUG(Indent -= 2);
|
|
|
|
return ResNode;
|
|
}
|