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e49dd688ba
candidates with coldcc attribute. This recommits r322721 reverted due to sanitizer memory leak build bot failures. Original commit message: This patch adds support for the coldcc calling convention for Power. This changes the set of non-volatile registers. It includes a pass to stress test the implementation by marking all static directly called functions with the coldcc attribute through the option -enable-coldcc-stress-test. It also includes an option, -ppc-enable-coldcc, to add the coldcc attribute to functions which are cold at all call sites based on BlockFrequencyInfo when the containing function does not call any non cold functions. Differential Revision: https://reviews.llvm.org/D38413 llvm-svn: 323778
43 lines
1.8 KiB
LLVM
43 lines
1.8 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefix=COLDCC
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%struct.MyStruct = type { i32, i32, i32, i32 }
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@caller.s = internal unnamed_addr global %struct.MyStruct zeroinitializer, align 8
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define signext i32 @caller(i32 signext %a, i32 signext %b, i32 signext %cold) {
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entry:
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; COLDCC: bl callee
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; COLDCC: ld 4, 40(1)
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; COLDCC: ld 5, 32(1)
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%call = tail call coldcc { i64, i64 } @callee(i32 signext %a, i32 signext %b)
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%0 = extractvalue { i64, i64 } %call, 0
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%1 = extractvalue { i64, i64 } %call, 1
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store i64 %0, i64* bitcast (%struct.MyStruct* @caller.s to i64*), align 8
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store i64 %1, i64* bitcast (i32* getelementptr inbounds (%struct.MyStruct, %struct.MyStruct* @caller.s, i64 0, i32 2) to i64*), align 8
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%2 = lshr i64 %1, 32
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%3 = trunc i64 %2 to i32
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%sub = sub nsw i32 0, %3
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ret i32 %sub
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}
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define internal coldcc { i64, i64 } @callee(i32 signext %a, i32 signext %b) {
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entry:
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; COLDCC: std {{[0-9]+}}, 0(3)
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; COLDCC: std {{[0-9]+}}, 8(3)
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%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r6},~{r7},~{r8},~{r9},~{r10}"(i32 %a, i32 %b)
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%mul = mul nsw i32 %a, 3
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%1 = mul i32 %b, -5
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%add = add i32 %1, %mul
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%sub = add i32 %add, %0
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%mul5 = mul nsw i32 %b, %a
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%add6 = add nsw i32 %sub, %mul5
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%retval.sroa.0.0.insert.ext = zext i32 %0 to i64
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%retval.sroa.3.8.insert.ext = zext i32 %sub to i64
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%retval.sroa.3.12.insert.ext = zext i32 %add6 to i64
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%retval.sroa.3.12.insert.shift = shl nuw i64 %retval.sroa.3.12.insert.ext, 32
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%retval.sroa.3.12.insert.insert = or i64 %retval.sroa.3.12.insert.shift, %retval.sroa.3.8.insert.ext
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%.fca.0.insert = insertvalue { i64, i64 } undef, i64 %retval.sroa.0.0.insert.ext, 0
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%.fca.1.insert = insertvalue { i64, i64 } %.fca.0.insert, i64 %retval.sroa.3.12.insert.insert, 1
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ret { i64, i64 } %.fca.1.insert
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}
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