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41072ed0b6
Up until Power9, the performance profile for rlwinm., rldicl. and andi. looked more or less equivalent. However with Power9, the rotates are still 2-way cracked whereas the and-immediate is not. This patch just ensures that we don't emit record-form rotates when an andi. is adequate. As first pointed out by Carrot in https://bugs.llvm.org/show_bug.cgi?id=30833 (this patch is a fix for that PR). Differential Revision: https://reviews.llvm.org/D43977 llvm-svn: 326736
58 lines
1.3 KiB
LLVM
58 lines
1.3 KiB
LLVM
; RUN: llc -verify-machineinstrs -O2 < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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; CHECK-LABEL: test1
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define i8 @test1(i32 %a) {
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entry:
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; CHECK-NOT: rlwinm {{{[0-9]+}}}, {{[0-9]+}}, 0, 24, 27
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; CHECK: andi. [[REG:[0-9]+]], {{[0-9]+}}, 240
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; CHECK-NOT: cmplwi [[REG]], 0
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; CHECK: beq 0
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%0 = and i32 %a, 240
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%1 = icmp eq i32 %0, 0
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br i1 %1, label %eq0, label %neq0
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eq0:
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ret i8 102
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neq0:
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ret i8 116
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}
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; CHECK-LABEL: test2
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define i8 @test2(i32 %a) {
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entry:
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; CHECK: rlwinm [[REG:[0-9]+]], {{[0-9]+}}, 0, 28, 23
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; CHECK: cmplwi [[REG]], 0
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; CHECK: beq 0
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%0 = and i32 %a, -241
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%1 = icmp eq i32 %0, 0
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br i1 %1, label %eq0, label %neq0
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eq0:
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ret i8 102
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neq0:
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ret i8 116
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}
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declare {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 %b)
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; CHECK-LABEL: test3
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define i8 @test3(i32 %a, i32 %b) {
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entry:
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; CHECK-NOT: rlwnm {{{[0-9]+}}}, {{[0-9]+}}, {{{[0-9]+}}}, 28, 31
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; CHECK: rlwnm. [[REG:[0-9]+]], {{[0-9]+}}, 4, 28, 31
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; CHECK-NOT: cmplwi [[REG]], 0
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; CHECK: beq 0
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%left = shl i32 %a, %b
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%res = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 32, i32 %b)
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%right_amount = extractvalue {i32, i1} %res, 0
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%right = lshr i32 %a, %right_amount
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%0 = or i32 %left, %right
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%1 = and i32 %0, 15
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%2 = icmp eq i32 %1, 0
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br i1 %2, label %eq0, label %neq0
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eq0:
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ret i8 102
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neq0:
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ret i8 116
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}
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