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3f9ad6b478
This re-commits everything that was pulled in r314244. The transformation is off by default (patch to enable it to follow). The code is refactored to have a single entry-point and provide fine-grained control over patterns that it selects. This patch also fixes the bugs in the original code. Everything that failed with the original patch has been re-tested with this patch (with the transformation turned on). So the patch to turn this on is soon to follow. Differential Revision: https://reviews.llvm.org/D38575 llvm-svn: 319434
118 lines
3.4 KiB
LLVM
118 lines
3.4 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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@glob = common local_unnamed_addr global i8 0, align 1
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_ileuc(i8 zeroext %a, i8 zeroext %b) {
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entry:
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%cmp = icmp ule i8 %a, %b
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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; CHECK-LABEL: test_ileuc:
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; CHECK: sub [[REG1:r[0-9]+]], r4, r3
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; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
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; CHECK-NEXT: xori r3, [[REG2]], 1
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_ileuc_sext(i8 zeroext %a, i8 zeroext %b) {
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entry:
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%cmp = icmp ule i8 %a, %b
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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; CHECK-LABEL: @test_ileuc_sext
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; CHECK: sub [[REG1:r[0-9]+]], r4, r3
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; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
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; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_ileuc_z(i8 zeroext %a) {
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entry:
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%cmp = icmp eq i8 %a, 0
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%conv1 = zext i1 %cmp to i32
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ret i32 %conv1
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; CHECK-LABEL: test_ileuc_z:
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; CHECK: cntlzw [[REG1:r[0-9]+]], r3
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; CHECK: srwi r3, [[REG1]], 5
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_ileuc_sext_z(i8 zeroext %a) {
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entry:
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%cmp = icmp ule i8 %a, 0
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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; CHECK-LABEL: @test_ileuc_sext_z
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; CHECK: cntlzw [[REG1:r[0-9]+]], r3
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; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
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; CHECK-NEXT: neg r3, [[REG2]]
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @test_ileuc_store(i8 zeroext %a, i8 zeroext %b) {
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entry:
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%cmp = icmp ule i8 %a, %b
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%conv3 = zext i1 %cmp to i8
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store i8 %conv3, i8* @glob
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ret void
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; CHECK-LABEL: test_ileuc_store:
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; CHECK: sub [[REG1:r[0-9]+]], r4, r3
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; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
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; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind
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define void @test_ileuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
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entry:
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%cmp = icmp ule i8 %a, %b
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%conv3 = sext i1 %cmp to i8
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store i8 %conv3, i8* @glob
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ret void
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; CHECK-LABEL: @test_ileuc_sext_store
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; CHECK: sub [[REG1:r[0-9]+]], r4, r3
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; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
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; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
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; CHECK: stb [[REG3]]
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind
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define void @test_ileuc_z_store(i8 zeroext %a) {
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entry:
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%cmp = icmp eq i8 %a, 0
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%conv2 = zext i1 %cmp to i8
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store i8 %conv2, i8* @glob
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ret void
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; CHECK-LABEL: test_ileuc_z_store:
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; CHECK: cntlzw [[REG1:r[0-9]+]], r3
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; CHECK: srwi {{r[0-9]+}}, [[REG1]], 5
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind
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define void @test_ileuc_sext_z_store(i8 zeroext %a) {
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entry:
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%cmp = icmp eq i8 %a, 0
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%conv2 = sext i1 %cmp to i8
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store i8 %conv2, i8* @glob
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ret void
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; CHECK-LABEL: @test_ileuc_sext_z_store
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; CHECK: cntlzw [[REG1:r[0-9]+]], r3
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; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
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; CHECK: neg [[REG3:r[0-9]+]], [[REG2]]
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; CHECK: stb [[REG3]]
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; CHECK: blr
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}
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