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fe9adb9248
This patch corresponds to review: https://reviews.llvm.org/D23155 This patch removes the VSHRC register class (based on D20310) and adds exploitation of the Power9 sub-word integer loads into VSX registers as well as vector sign extensions. The new instructions are useful for a few purposes: Int to Fp conversions of 1 or 2-byte values loaded from memory Building vectors of 1 or 2-byte integers with values loaded from memory Storing individual 1 or 2-byte elements from integer vectors This patch implements all of those uses. llvm-svn: 283190
66 lines
2.8 KiB
LLVM
66 lines
2.8 KiB
LLVM
; RUN: llc -mcpu=pwr7 -verify-machineinstrs < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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@.str1 = external unnamed_addr constant [5 x i8], align 1
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@.str10 = external unnamed_addr constant [9 x i8], align 1
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@.v2f64 = external unnamed_addr constant <2 x double>, align 16
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; Function Attrs: nounwind
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define void @main() #0 {
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; CHECK-LABEL: @main
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; Make sure that the stxvd2x passes -verify-machineinstrs
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; CHECK: stxvd2x
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entry:
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%val = load <2 x double>, <2 x double>* @.v2f64, align 16
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%0 = tail call <8 x i16> @llvm.ppc.altivec.vupkhsb(<16 x i8> <i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1>) #0
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%1 = tail call <8 x i16> @llvm.ppc.altivec.vupklsb(<16 x i8> <i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1>) #0
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br i1 false, label %if.then.i68.i, label %check.exit69.i
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if.then.i68.i: ; preds = %entry
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unreachable
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check.exit69.i: ; preds = %entry
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br i1 undef, label %if.then.i63.i, label %check.exit64.i
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if.then.i63.i: ; preds = %check.exit69.i
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tail call void (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str10, i64 0, i64 0), i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str1, i64 0, i64 0), <2 x double> %val) #0
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br label %check.exit64.i
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check.exit64.i: ; preds = %if.then.i63.i, %check.exit69.i
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%2 = tail call i32 @llvm.ppc.altivec.vcmpequh.p(i32 2, <8 x i16> %0, <8 x i16> <i16 0, i16 -1, i16 -1, i16 0, i16 0, i16 0, i16 -1, i16 0>) #0
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%tobool.i55.i = icmp eq i32 %2, 0
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br i1 %tobool.i55.i, label %if.then.i58.i, label %check.exit59.i
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if.then.i58.i: ; preds = %check.exit64.i
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unreachable
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check.exit59.i: ; preds = %check.exit64.i
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%3 = tail call i32 @llvm.ppc.altivec.vcmpequh.p(i32 2, <8 x i16> %1, <8 x i16> <i16 -1, i16 0, i16 0, i16 -1, i16 -1, i16 -1, i16 0, i16 -1>) #0
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%tobool.i50.i = icmp eq i32 %3, 0
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br i1 %tobool.i50.i, label %if.then.i53.i, label %check.exit54.i
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if.then.i53.i: ; preds = %check.exit59.i
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unreachable
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check.exit54.i: ; preds = %check.exit59.i
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unreachable
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}
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; Function Attrs: nounwind readnone
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declare <8 x i16> @llvm.ppc.altivec.vupkhsb(<16 x i8>) #1
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; Function Attrs: nounwind readnone
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declare <8 x i16> @llvm.ppc.altivec.vupklsb(<16 x i8>) #1
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; Function Attrs: nounwind
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declare void @printf(i8* nocapture readonly, ...) #0
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; Function Attrs: nounwind readnone
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declare i32 @llvm.ppc.altivec.vcmpequh.p(i32, <8 x i16>, <8 x i16>) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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