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16f8ead77d
Summary: Fix case where a pre-inc/dec load/store would not be formed if the add/sub that forms the inc/dec part of the operation was the first instruction in the block being examined. Reviewers: mcrosier, jmolloy, t.p.northover, junbuml Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D16785 llvm-svn: 260275
30 lines
820 B
LLVM
30 lines
820 B
LLVM
; RUN: llc < %s -mtriple=arm64-apple-ios | FileCheck %s
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; CHECK-LABEL: _test:
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; CHECK: fmov.2d v0, #2.00000000
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; CHECK: str q0, [sp, #-16]!
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; CHECK: mov x8, sp
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; CHECK: ldr s0, [x8, w1, sxtw #2]
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; CHECK: str s0, [x0]
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define void @test(float * %p1, i32 %v1) {
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entry:
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%v2 = extractelement <3 x float> <float 0.000000e+00, float 2.000000e+00, float 0.000000e+00>, i32 %v1
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store float %v2, float* %p1, align 4
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ret void
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}
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; CHECK-LABEL: _test2
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; CHECK: movi.16b v0, #0x3f
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; CHECK: str q0, [sp, #-16]!
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; CHECK: mov x8, sp
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; CHECK: ldr s0, [x8, w1, sxtw #2]
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; CHECK: str s0, [x0]
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define void @test2(float * %p1, i32 %v1) {
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entry:
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%v2 = extractelement <3 x float> <float 0.7470588088035583, float 0.7470588088035583, float 0.7470588088035583>, i32 %v1
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store float %v2, float* %p1, align 4
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ret void
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}
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