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876dc10c73
A linker optimization is available on PowerPC for GOT indirect PCRelative loads. The idea is that we can mark a usual GOT indirect load: pld 3, vec@got@pcrel(0), 1 lwa 3, 4(3) With a relocation to say that if we don't need to go through the GOT we can let the linker further optimize this and replace a load with a nop. pld 3, vec@got@pcrel(0), 1 .Lpcrel1: .reloc .Lpcrel1-8,R_PPC64_PCREL_OPT,.-(.Lpcrel1-8) lwa 3, 4(3) This patch adds the logic that allows the compiler to add the R_PPC64_PCREL_OPT. Reviewers: nemanjai, lei, hfinkel, sfertile, efriedma, tstellar, grosbach Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D79864
88 lines
3.4 KiB
LLVM
88 lines
3.4 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s --check-prefix=CHECK-S
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: --filetype=obj < %s | \
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; RUN: llvm-objdump --mcpu=pwr10 -dr - | FileCheck %s --check-prefix=CHECK-O
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; RUN: llc -verify-machineinstrs -target-abi=elfv2 -mtriple=powerpc64-- \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s --check-prefix=CHECK-S
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; RUN: llc -verify-machineinstrs -target-abi=elfv2 -mtriple=powerpc64-- \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: --filetype=obj < %s | \
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; RUN: llvm-objdump --mcpu=pwr10 -dr - | FileCheck %s --check-prefix=CHECK-O
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@array1 = external local_unnamed_addr global [10 x i32], align 4
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@array2 = common dso_local local_unnamed_addr global [10 x i32] zeroinitializer, align 4
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define dso_local signext i32 @getElementLocal7() local_unnamed_addr {
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; CHECK-S-LABEL: getElementLocal7:
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; CHECK-S: # %bb.0: # %entry
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; CHECK-S-NEXT: plwa r3, array2@PCREL+28(0), 1
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; CHECK-S-NEXT: blr
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; CHECK-O-LABEL: <getElementLocal7>:
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; CHECK-O: plwa 3, 0(0), 1
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; CHECK-O-NEXT: R_PPC64_PCREL34 array2+0x1c
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; CHECK-O-NEXT: blr
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entry:
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%0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @array2, i64 0, i64 7), align 4
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ret i32 %0
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}
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define dso_local signext i32 @getElementLocalNegative() local_unnamed_addr {
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; CHECK-S-LABEL: getElementLocalNegative:
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; CHECK-S: # %bb.0: # %entry
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; CHECK-S-NEXT: plwa r3, array2@PCREL-8(0), 1
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; CHECK-S-NEXT: blr
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; CHECK-O-LABEL: <getElementLocalNegative>:
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; CHECK-O: plwa 3, 0(0), 1
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; CHECK-O-NEXT: R_PPC64_PCREL34 array2-0x8
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; CHECK-O-NEXT: blr
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entry:
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%0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @array2, i64 0, i64 -2), align 4
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ret i32 %0
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}
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define dso_local signext i32 @getElementExtern4() local_unnamed_addr {
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; CHECK-S-LABEL: getElementExtern4:
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; CHECK-S: # %bb.0: # %entry
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; CHECK-S-NEXT: pld r3, array1@got@pcrel(0), 1
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; CHECK-S-NEXT: .Lpcrel:
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; CHECK-S-NEXT: .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8)
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; CHECK-S-NEXT: lwa r3, 16(r3)
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; CHECK-S-NEXT: blr
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; CHECK-O-LABEL: <getElementExtern4>:
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; CHECK-O: pld 3, 0(0), 1
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; CHECK-O-NEXT: R_PPC64_GOT_PCREL34 array1
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; CHECK-O-NEXT: R_PPC64_PCREL_OPT *ABS*+0x8
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; CHECK-O: lwa 3, 16(3)
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; CHECK-O-NEXT: blr
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entry:
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%0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @array1, i64 0, i64 4), align 4
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ret i32 %0
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}
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define dso_local signext i32 @getElementExternNegative() local_unnamed_addr {
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; CHECK-S-LABEL: getElementExternNegative:
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; CHECK-S: # %bb.0: # %entry
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; CHECK-S-NEXT: pld r3, array1@got@pcrel(0), 1
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; CHECK-S-NEXT: .Lpcrel0:
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; CHECK-S-NEXT: .reloc .Lpcrel0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel0-8)
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; CHECK-S-NEXT: lwa r3, -4(r3)
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; CHECK-S-NEXT: blr
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; CHECK-O-LABEL: <getElementExternNegative>:
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; CHECK-O: pld 3, 0(0), 1
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; CHECK-O-NEXT: R_PPC64_GOT_PCREL34 array1
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; CHECK-O-NEXT: R_PPC64_PCREL_OPT *ABS*+0x8
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; CHECK-O: lwa 3, -4(3)
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; CHECK-O-NEXT: blr
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entry:
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%0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @array1, i64 0, i64 -1), align 4
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ret i32 %0
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}
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