Evan Cheng 9946443460 Fix @llvm.frameaddress codegen. FP elimination optimization should be disabled when frame address is desired. Also add support for depth > 0. ... llvm-svn: 56683		2008-09-26 19:48:35 +00:00
..
CallingConvLower.cpp	Add "inreg" field to CallSDNode (doesn't increase	2008-09-26 19:31:26 +00:00
CMakeLists.txt
DAGCombiner.cpp	Reapplying r56550	2008-09-24 10:25:02 +00:00
FastISel.cpp	Support for i1 XOR in FastISel. It is actually safe because	2008-09-25 17:22:52 +00:00
LegalizeDAG.cpp	Add "inreg" field to CallSDNode (doesn't increase	2008-09-26 19:31:26 +00:00
LegalizeFloatTypes.cpp
LegalizeIntegerTypes.cpp
LegalizeTypes.cpp	Add "inreg" field to CallSDNode (doesn't increase	2008-09-26 19:31:26 +00:00
LegalizeTypes.h
LegalizeTypesGeneric.cpp
LegalizeVectorTypes.cpp
Makefile
ScheduleDAG.cpp
ScheduleDAGEmit.cpp	Next round of earlyclobber handling. Approach the	2008-09-24 01:07:17 +00:00
ScheduleDAGFast.cpp	Replace the LiveRegs SmallSet with a simple counter that keeps	2008-09-23 18:50:48 +00:00
ScheduleDAGList.cpp
ScheduleDAGRRList.cpp	Replace the LiveRegs SmallSet with a simple counter that keeps	2008-09-23 18:50:48 +00:00
SelectionDAG.cpp	Add "inreg" field to CallSDNode (doesn't increase	2008-09-26 19:31:26 +00:00
SelectionDAGBuild.cpp	Fix @llvm.frameaddress codegen. FP elimination optimization should be disabled when frame address is desired. Also add support for depth > 0.	2008-09-26 19:48:35 +00:00
SelectionDAGBuild.h	Remove SelectionDag early allocation of registers	2008-09-24 23:13:09 +00:00
SelectionDAGISel.cpp	Large mechanical patch.	2008-09-25 21:00:45 +00:00
SelectionDAGPrinter.cpp
TargetLowering.cpp	Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc.	2008-09-24 00:05:32 +00:00