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392d2cbdcc
operand and one of them has a single use that is a live out copy, favor the one that is live out. Otherwise it will be difficult to eliminate the copy if the instruction is a loop induction variable update. e.g. BB: sub r1, r3, #1 str r0, [r2, r3] mov r3, r1 cmp bne BB => BB: str r0, [r2, r3] sub r3, r3, #1 cmp bne BB This fixed the recent 256.bzip2 regression. llvm-svn: 117675
81 lines
3.9 KiB
LLVM
81 lines
3.9 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | FileCheck %s
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define void @fht(float* nocapture %fz, i16 signext %n) nounwind {
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; CHECK: fht:
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entry:
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br label %bb5
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bb5: ; preds = %bb5, %entry
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; CHECK: %bb5
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; CHECK: bne
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br i1 undef, label %bb5, label %bb.nph
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bb.nph: ; preds = %bb5
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br label %bb7
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; Loop preheader
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; CHECK: vmov.f32
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; CHECK: vsub.f32
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; CHECK: vadd.f32
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; CHECK: vmul.f32
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bb7: ; preds = %bb9, %bb.nph
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%s1.02 = phi float [ undef, %bb.nph ], [ %35, %bb9 ] ; <float> [#uses=3]
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%tmp79 = add i32 undef, undef ; <i32> [#uses=1]
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%tmp53 = sub i32 undef, undef ; <i32> [#uses=1]
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%0 = fadd float 0.000000e+00, 1.000000e+00 ; <float> [#uses=2]
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%1 = fmul float 0.000000e+00, 0.000000e+00 ; <float> [#uses=2]
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br label %bb8
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bb8: ; preds = %bb8, %bb7
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; CHECK: %bb8
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; CHECK-NOT: vmov.f32
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; CHECK: blt
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%tmp54 = add i32 0, %tmp53 ; <i32> [#uses=0]
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%fi.1 = getelementptr float* %fz, i32 undef ; <float*> [#uses=2]
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%tmp80 = add i32 0, %tmp79 ; <i32> [#uses=1]
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%scevgep81 = getelementptr float* %fz, i32 %tmp80 ; <float*> [#uses=1]
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%2 = load float* undef, align 4 ; <float> [#uses=1]
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%3 = fmul float %2, %1 ; <float> [#uses=1]
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%4 = load float* null, align 4 ; <float> [#uses=2]
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%5 = fmul float %4, %0 ; <float> [#uses=1]
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%6 = fsub float %3, %5 ; <float> [#uses=1]
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%7 = fmul float %4, %1 ; <float> [#uses=1]
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%8 = fadd float undef, %7 ; <float> [#uses=2]
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%9 = load float* %fi.1, align 4 ; <float> [#uses=2]
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%10 = fsub float %9, %8 ; <float> [#uses=1]
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%11 = fadd float %9, %8 ; <float> [#uses=1]
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%12 = fsub float 0.000000e+00, %6 ; <float> [#uses=1]
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%13 = fsub float 0.000000e+00, undef ; <float> [#uses=2]
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%14 = fmul float undef, %0 ; <float> [#uses=1]
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%15 = fadd float %14, undef ; <float> [#uses=2]
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%16 = load float* %scevgep81, align 4 ; <float> [#uses=2]
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%17 = fsub float %16, %15 ; <float> [#uses=1]
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%18 = fadd float %16, %15 ; <float> [#uses=2]
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%19 = load float* undef, align 4 ; <float> [#uses=2]
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%20 = fsub float %19, %13 ; <float> [#uses=2]
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%21 = fadd float %19, %13 ; <float> [#uses=1]
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%22 = fmul float %s1.02, %18 ; <float> [#uses=1]
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%23 = fmul float 0.000000e+00, %20 ; <float> [#uses=1]
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%24 = fsub float %22, %23 ; <float> [#uses=1]
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%25 = fmul float 0.000000e+00, %18 ; <float> [#uses=1]
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%26 = fmul float %s1.02, %20 ; <float> [#uses=1]
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%27 = fadd float %25, %26 ; <float> [#uses=1]
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%28 = fadd float %11, %27 ; <float> [#uses=1]
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store float %28, float* %fi.1, align 4
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%29 = fadd float %12, %24 ; <float> [#uses=1]
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store float %29, float* null, align 4
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%30 = fmul float 0.000000e+00, %21 ; <float> [#uses=1]
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%31 = fmul float %s1.02, %17 ; <float> [#uses=1]
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%32 = fsub float %30, %31 ; <float> [#uses=1]
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%33 = fsub float %10, %32 ; <float> [#uses=1]
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store float %33, float* undef, align 4
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%34 = icmp slt i32 undef, undef ; <i1> [#uses=1]
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br i1 %34, label %bb8, label %bb9
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bb9: ; preds = %bb8
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; CHECK: %bb9
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; CHECK: vmov.f32
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%35 = fadd float 0.000000e+00, undef ; <float> [#uses=1]
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br label %bb7
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}
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