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Summary: This adds a new attribute which targets can set in TableGen which causes a function to be generated which matches register alternative names. This is very similar to `ShouldEmitMatchRegisterName`, except it works on alt names. This patch is currently used by the out of tree part of the AVR backend. It reduces code duplication greatly, and has the effect that you do not need to hardcode altname to register mappings in C++. It will not work on targets which have registers which share the same aliases. Reviewers: stoklund, arsenm, dsanders, hfinkel, vkalintiris Subscribers: hfinkel, dylanmckay, llvm-commits Differential Revision: http://reviews.llvm.org/D16312 llvm-svn: 259636 |
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| .. | ||
| bugpoint | ||
| count | ||
| crosstool | ||
| emacs | ||
| FileCheck | ||
| fpcmp | ||
| git | ||
| git-svn | ||
| jedit | ||
| kate | ||
| KillTheDoctor | ||
| lint | ||
| lit | ||
| llvm-build | ||
| llvm-lit | ||
| Misc | ||
| not | ||
| PerfectShuffle | ||
| release | ||
| TableGen | ||
| Target/ARM | ||
| testgen | ||
| textmate | ||
| unittest | ||
| valgrind | ||
| vim | ||
| yaml-bench | ||
| bisect | ||
| check-each-file | ||
| clang-parse-diagnostics-file | ||
| codegen-diff | ||
| countloc.sh | ||
| create_ladder_graph.py | ||
| DSAclean.py | ||
| DSAextract.py | ||
| findmisopt | ||
| findoptdiff | ||
| findsym.pl | ||
| GenLibDeps.pl | ||
| GetRepositoryPath | ||
| GetSourceVersion | ||
| getsrcs.sh | ||
| lldbDataFormatters.py | ||
| llvm-compilers-check | ||
| llvm-native-gxx | ||
| llvm.grm | ||
| llvm.natvis | ||
| LLVMBuild.txt | ||
| llvmdo | ||
| llvmgrep | ||
| makellvm | ||
| schedcover.py | ||
| shuffle_fuzz.py | ||
| sort_includes.py | ||
| test_debuginfo.pl | ||
| update_llc_test_checks.py | ||
| UpdateCMakeLists.pl | ||
| wciia.py | ||