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The current demand propagator for addition will mark all input bits at and right of the alive output bit as alive. But carry won't propagate beyond a bit for which both operands are zero (or one/zero in the case of subtraction) so a more accurate answer is possible given known bits. I derived a propagator by working through truth tables and using a bit-reversed addition to make demand ripple to the right, but I'm not sure how to make a convincing argument for its correctness in the comments yet. Nevertheless, here's a minimal implementation and test to get feedback. This would help in a situation where, for example, four bytes (<128) packed into an int are added with four others SIMD-style but only one of the four results is actually read. Known A: 0_______0_______0_______0_______ Known B: 0_______0_______0_______0_______ AOut: 00000000001000000000000000000000 AB, current: 00000000001111111111111111111111 AB, patch: 00000000001111111000000000000000 Committed on behalf of: @rrika (Erika) Differential Revision: https://reviews.llvm.org/D72423
67 lines
2.4 KiB
C++
67 lines
2.4 KiB
C++
//===- DemandedBitsTest.cpp - DemandedBits tests --------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Analysis/DemandedBits.h"
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#include "../Support/KnownBitsTest.h"
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#include "llvm/Support/KnownBits.h"
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#include "gtest/gtest.h"
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using namespace llvm;
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namespace {
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template <typename Fn1, typename Fn2>
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static void TestBinOpExhaustive(Fn1 PropagateFn, Fn2 EvalFn) {
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unsigned Bits = 4;
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unsigned Max = 1 << Bits;
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ForeachKnownBits(Bits, [&](const KnownBits &Known1) {
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ForeachKnownBits(Bits, [&](const KnownBits &Known2) {
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for (unsigned AOut_ = 0; AOut_ < Max; AOut_++) {
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APInt AOut(Bits, AOut_);
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APInt AB1 = PropagateFn(0, AOut, Known1, Known2);
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APInt AB2 = PropagateFn(1, AOut, Known1, Known2);
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{
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// If the propagator claims that certain known bits
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// didn't matter, check it doesn't change its mind
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// when they become unknown.
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KnownBits Known1Redacted;
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KnownBits Known2Redacted;
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Known1Redacted.Zero = Known1.Zero & AB1;
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Known1Redacted.One = Known1.One & AB1;
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Known2Redacted.Zero = Known2.Zero & AB2;
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Known2Redacted.One = Known2.One & AB2;
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APInt AB1R = PropagateFn(0, AOut, Known1Redacted, Known2Redacted);
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APInt AB2R = PropagateFn(1, AOut, Known1Redacted, Known2Redacted);
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EXPECT_EQ(AB1, AB1R);
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EXPECT_EQ(AB2, AB2R);
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}
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ForeachNumInKnownBits(Known1, [&](APInt Value1) {
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ForeachNumInKnownBits(Known2, [&](APInt Value2) {
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APInt ReferenceResult = EvalFn((Value1 & AB1), (Value2 & AB2));
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APInt Result = EvalFn(Value1, Value2);
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EXPECT_EQ(Result & AOut, ReferenceResult & AOut);
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});
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});
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}
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});
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});
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}
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TEST(DemandedBitsTest, Add) {
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TestBinOpExhaustive(DemandedBits::determineLiveOperandBitsAdd,
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[](APInt N1, APInt N2) -> APInt { return N1 + N2; });
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}
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TEST(DemandedBitsTest, Sub) {
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TestBinOpExhaustive(DemandedBits::determineLiveOperandBitsSub,
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[](APInt N1, APInt N2) -> APInt { return N1 - N2; });
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}
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} // anonymous namespace
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