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llvm-mirror/test/CodeGen
Matheus Almeida 67244395fb [mips][msa] Add fill.d instruction.
This instruction is only available on Mips64 cores
that implement the MSA ASE.

llvm-svn: 200400
2014-01-29 15:12:02 +00:00
..
AArch64 [AArch64 NEON] Lower SELECT_CC with vector operand. 2014-01-29 01:57:30 +00:00
ARM Enable EHABI by default 2014-01-29 11:50:56 +00:00
CPP Begin adding docs and IR-level support for the inalloca attribute 2013-12-19 02:14:12 +00:00
Generic Additional fix for 200201: due to dependence on bitwidth test was moved to X86 directory. 2014-01-27 09:43:10 +00:00
Hexagon
Inputs
Mips [mips][msa] Add fill.d instruction. 2014-01-29 15:12:02 +00:00
MSP430 Fix known typos 2014-01-24 17:20:08 +00:00
NVPTX [NVPTX] Fix emitting aggregate parameters 2014-01-28 18:35:29 +00:00
PowerPC Handle spilling the PPC GPRC_NOR0 register class 2014-01-28 05:32:58 +00:00
R600 R600/SI: Add pattern for truncating i32 to i1 2014-01-28 03:01:16 +00:00
SPARC [Sparc] Use %r_disp32 for pc_rel entries in FDE as well. 2014-01-29 06:59:20 +00:00
SystemZ XFAIL test/CodeGen/SystemZ/alias-01.ll which requires CodeGen TBAA 2014-01-25 19:31:44 +00:00
Thumb CodeGen: Stop treating vectors as aggregates 2014-01-21 22:46:46 +00:00
Thumb2 Enable EHABI by default 2014-01-29 11:50:56 +00:00
X86 Use a raw_stream to implement the mangler. 2014-01-29 02:30:38 +00:00
XCore Fix broken CHECK lines. 2014-01-11 21:06:00 +00:00