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251919f579
LLVM normally prefers to minimize the number of bits set in an AND immediate, but that doesn't always match the available ARM instructions. In Thumb1 mode, prefer uxtb or uxth where possible; otherwise, prefer a two-instruction sequence movs+ands or movs+bics. Some potential improvements outlined in ARMTargetLowering::targetShrinkDemandedConstant, but seems to work pretty well already. The ARMISelDAGToDAG fix ensures we don't generate an invalid UBFX instruction due to a larger-than-expected mask. (It's orthogonal, in some sense, but as far as I can tell it's either impossible or nearly impossible to reproduce the bug without this change.) According to my testing, this seems to consistently improve codesize by a small amount by forming bic more often for ISD::AND with an immediate. Differential Revision: https://reviews.llvm.org/D50030 llvm-svn: 339472
110 lines
2.1 KiB
LLVM
110 lines
2.1 KiB
LLVM
; RUN: llc -mtriple=thumbv7m-linux-gnu < %s | FileCheck %s --check-prefix=CHECK --check-prefix=T2
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; RUN: llc -mtriple=thumbv6m-linux-gnu < %s | FileCheck %s --check-prefix=CHECK --check-prefix=T1
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; CHECK-LABEL: single_bit:
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; CHECK: lsls r0, r0, #23
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; T2-NEXT: mov
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; T2-NEXT: it
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; T1-NEXT: bmi
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define i32 @single_bit(i32 %p) {
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%a = and i32 %p, 256
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%b = icmp eq i32 %a, 0
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br i1 %b, label %true, label %false
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true:
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ret i32 1
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false:
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ret i32 2
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}
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; CHECK-LABEL: single_bit_multi_use:
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; CHECK: lsls r0, r0, #23
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; T2-NEXT: mov
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; T2-NEXT: it
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; T1-NEXT: bmi
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define i32 @single_bit_multi_use(i32 %p, i32* %z) {
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store i32 %p, i32* %z
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%a = and i32 %p, 256
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%b = icmp eq i32 %a, 0
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br i1 %b, label %true, label %false
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true:
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ret i32 1
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false:
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ret i32 2
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}
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; CHECK-LABEL: multi_bit_lsb_ubfx:
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; CHECK: lsls r0, r0, #24
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; T2-NEXT: mov
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; T2-NEXT: it
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; T1-NEXT: beq
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define i32 @multi_bit_lsb_ubfx(i32 %p) {
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%a = and i32 %p, 255
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%b = icmp eq i32 %a, 0
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br i1 %b, label %true, label %false
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true:
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ret i32 1
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false:
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ret i32 2
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}
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; CHECK-LABEL: multi_bit_msb:
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; CHECK: lsrs r0, r0, #24
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; T2-NEXT: mov
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; T2-NEXT: it
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; T1-NEXT: beq
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define i32 @multi_bit_msb(i32 %p) {
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%a = and i32 %p, 4278190080 ; 0xff000000
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%b = icmp eq i32 %a, 0
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br i1 %b, label %true, label %false
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true:
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ret i32 1
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false:
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ret i32 2
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}
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; CHECK-LABEL: multi_bit_nosb:
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; T1: lsls r0, r0, #8
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; T1-NEXT: lsrs r0, r0, #24
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; T2: tst.w
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; T2-NEXT: it
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; T1-NEXT: beq
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define i32 @multi_bit_nosb(i32 %p) {
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%a = and i32 %p, 16711680 ; 0x00ff0000
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%b = icmp eq i32 %a, 0
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br i1 %b, label %true, label %false
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true:
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ret i32 1
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false:
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ret i32 2
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}
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; CHECK-LABEL: i16_cmpz:
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; T1: uxth r0, r0
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; T1-NEXT: lsrs r0, r0, #9
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; T1-NEXT: bne
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; T2: uxth r0, r0
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; T2-NEXT: movs r2, #0
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; T2-NEXT: cmp.w r2, r0, lsr #9
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define void @i16_cmpz(i16 %x, void (i32)* %foo) {
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entry:
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%cmp = icmp ult i16 %x, 512
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void %foo(i32 0) #1
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret void
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}
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