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https://github.com/RPCS3/llvm-mirror.git
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a515304bf7
Summary: Half-precision floating point arguments and returns are currently promoted to either float or int32 in clang's CodeGen and there's no existing support for the lowering of `half` arguments and returns from IR in AArch32's backend. Such frontend coercions, implemented as coercion through memory in clang, can cause a series of issues in argument lowering, as causing arguments to be stored on the wrong bits on big-endian architectures and incurring in missing overflow detections in the return of certain functions. This patch introduces the handling of half-precision arguments and returns in the backend using the actual "half" type on the IR. Using the "half" type the backend is able to properly enforce the AAPCS' directions for those arguments, making sure they are stored on the proper bits of the registers and performing the necessary floating point convertions. Reviewers: rjmccall, olista01, asl, efriedma, ostannard, SjoerdMeijer Reviewed By: ostannard Subscribers: stuij, hiraditya, dmgreen, llvm-commits, chill, dnsampaio, danielkiss, kristof.beyls, cfe-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D75169
548 lines
16 KiB
LLVM
548 lines
16 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=armv8-eabi -mattr=+fullfp16 | FileCheck %s
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; RUN: llc < %s -mtriple thumbv7a -mattr=+fullfp16 | FileCheck %s
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define half @fp16_vminnm_o(half %a, half %b) {
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; CHECK-LABEL: fp16_vminnm_o:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f16 s0, r1
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; CHECK-NEXT: vmov.f16 s2, r0
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; CHECK-NEXT: vcmp.f16 s0, s2
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: vselgt.f16 s0, s2, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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entry:
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%cmp = fcmp olt half %a, %b
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%cond = select i1 %cmp, half %a, half %b
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ret half %cond
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}
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define half @fp16_vminnm_o_rev(half %a, half %b) {
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; CHECK-LABEL: fp16_vminnm_o_rev:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f16 s0, r1
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; CHECK-NEXT: vmov.f16 s2, r0
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; CHECK-NEXT: vcmp.f16 s2, s0
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: vselgt.f16 s0, s2, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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entry:
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%cmp = fcmp ogt half %a, %b
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%cond = select i1 %cmp, half %a, half %b
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ret half %cond
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}
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define half @fp16_vminnm_u(half %a, half %b) {
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; CHECK-LABEL: fp16_vminnm_u:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f16 s0, r0
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; CHECK-NEXT: vmov.f16 s2, r1
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; CHECK-NEXT: vcmp.f16 s0, s2
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: vselge.f16 s0, s2, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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entry:
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%cmp = fcmp ult half %a, %b
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%cond = select i1 %cmp, half %a, half %b
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ret half %cond
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}
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define half @fp16_vminnm_ule(half %a, half %b) {
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; CHECK-LABEL: fp16_vminnm_ule:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f16 s0, r0
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; CHECK-NEXT: vmov.f16 s2, r1
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; CHECK-NEXT: vcmp.f16 s0, s2
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: vselgt.f16 s0, s2, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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entry:
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%cmp = fcmp ule half %a, %b
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%cond = select i1 %cmp, half %a, half %b
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ret half %cond
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}
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define half @fp16_vminnm_u_rev(half %a, half %b) {
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; CHECK-LABEL: fp16_vminnm_u_rev:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f16 s0, r1
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; CHECK-NEXT: vmov.f16 s2, r0
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; CHECK-NEXT: vcmp.f16 s0, s2
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: vselge.f16 s0, s2, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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entry:
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%cmp = fcmp ugt half %a, %b
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%cond = select i1 %cmp, half %b, half %a
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ret half %cond
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}
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define half @fp16_vmaxnm_o(half %a, half %b) {
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; CHECK-LABEL: fp16_vmaxnm_o:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f16 s0, r1
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; CHECK-NEXT: vmov.f16 s2, r0
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; CHECK-NEXT: vcmp.f16 s2, s0
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: vselgt.f16 s0, s2, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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entry:
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%cmp = fcmp ogt half %a, %b
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%cond = select i1 %cmp, half %a, half %b
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ret half %cond
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}
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define half @fp16_vmaxnm_oge(half %a, half %b) {
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; CHECK-LABEL: fp16_vmaxnm_oge:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f16 s0, r1
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; CHECK-NEXT: vmov.f16 s2, r0
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; CHECK-NEXT: vcmp.f16 s2, s0
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: vselge.f16 s0, s2, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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entry:
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%cmp = fcmp oge half %a, %b
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%cond = select i1 %cmp, half %a, half %b
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ret half %cond
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}
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define half @fp16_vmaxnm_o_rev(half %a, half %b) {
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; CHECK-LABEL: fp16_vmaxnm_o_rev:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f16 s0, r0
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; CHECK-NEXT: vmov.f16 s2, r1
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; CHECK-NEXT: vcmp.f16 s2, s0
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: vselgt.f16 s0, s2, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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entry:
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%cmp = fcmp olt half %a, %b
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%cond = select i1 %cmp, half %b, half %a
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ret half %cond
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}
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define half @fp16_vmaxnm_ole_rev(half %a, half %b) {
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; CHECK-LABEL: fp16_vmaxnm_ole_rev:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f16 s0, r0
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; CHECK-NEXT: vmov.f16 s2, r1
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; CHECK-NEXT: vcmp.f16 s2, s0
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: vselge.f16 s0, s2, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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entry:
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%cmp = fcmp ole half %a, %b
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%cond = select i1 %cmp, half %b, half %a
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ret half %cond
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}
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define half @fp16_vmaxnm_u(half %a, half %b) {
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; CHECK-LABEL: fp16_vmaxnm_u:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f16 s0, r0
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; CHECK-NEXT: vmov.f16 s2, r1
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; CHECK-NEXT: vcmp.f16 s2, s0
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: vselge.f16 s0, s2, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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entry:
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%cmp = fcmp ugt half %a, %b
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%cond = select i1 %cmp, half %a, half %b
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ret half %cond
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}
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define half @fp16_vmaxnm_uge(half %a, half %b) {
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; CHECK-LABEL: fp16_vmaxnm_uge:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f16 s0, r0
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; CHECK-NEXT: vmov.f16 s2, r1
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; CHECK-NEXT: vcmp.f16 s2, s0
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: vselgt.f16 s0, s2, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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entry:
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%cmp = fcmp uge half %a, %b
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%cond = select i1 %cmp, half %a, half %b
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ret half %cond
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}
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define half @fp16_vmaxnm_u_rev(half %a, half %b) {
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; CHECK-LABEL: fp16_vmaxnm_u_rev:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f16 s0, r1
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; CHECK-NEXT: vmov.f16 s2, r0
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; CHECK-NEXT: vcmp.f16 s2, s0
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: vselge.f16 s0, s2, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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entry:
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%cmp = fcmp ult half %a, %b
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%cond = select i1 %cmp, half %b, half %a
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ret half %cond
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}
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; known non-NaNs
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define half @fp16_vminnm_NNNo(half %a) {
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; CHECK-LABEL: fp16_vminnm_NNNo:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f16 s0, r0
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; CHECK-NEXT: vmov.f16 s2, #1.200000e+01
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; CHECK-NEXT: vminnm.f16 s0, s0, s2
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; CHECK-NEXT: vldr.16 s2, .LCPI12_0
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; CHECK-NEXT: vcmp.f16 s0, s2
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: vselgt.f16 s0, s2, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 1
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI12_0:
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; CHECK-NEXT: .short 0x5040 @ half 34
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entry:
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%cmp1 = fcmp olt half %a, 12.
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%cond1 = select i1 %cmp1, half %a, half 12.
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%cmp2 = fcmp olt half 34., %cond1
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%cond2 = select i1 %cmp2, half 34., half %cond1
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ret half %cond2
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}
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define half @fp16_vminnm_NNNo_rev(half %a) {
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; CHECK-LABEL: fp16_vminnm_NNNo_rev:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldr.16 s2, .LCPI13_0
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; CHECK-NEXT: vmov.f16 s0, r0
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; CHECK-NEXT: vcmp.f16 s0, s2
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: vselgt.f16 s0, s2, s0
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; CHECK-NEXT: vldr.16 s2, .LCPI13_1
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; CHECK-NEXT: vminnm.f16 s0, s0, s2
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 1
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI13_0:
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; CHECK-NEXT: .short 0x5300 @ half 56
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; CHECK-NEXT: .LCPI13_1:
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; CHECK-NEXT: .short 0x54e0 @ half 78
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entry:
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%cmp1 = fcmp ogt half %a, 56.
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%cond1 = select i1 %cmp1, half 56., half %a
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%cmp2 = fcmp ogt half 78., %cond1
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%cond2 = select i1 %cmp2, half %cond1, half 78.
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ret half %cond2
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}
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define half @fp16_vminnm_NNNu(half %b) {
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; CHECK-LABEL: fp16_vminnm_NNNu:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f16 s0, r0
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; CHECK-NEXT: vmov.f16 s2, #1.200000e+01
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; CHECK-NEXT: vminnm.f16 s0, s0, s2
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; CHECK-NEXT: vldr.16 s2, .LCPI14_0
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; CHECK-NEXT: vcmp.f16 s0, s2
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: vselge.f16 s0, s2, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 1
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI14_0:
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; CHECK-NEXT: .short 0x5040 @ half 34
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entry:
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%cmp1 = fcmp ult half 12., %b
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%cond1 = select i1 %cmp1, half 12., half %b
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%cmp2 = fcmp ult half %cond1, 34.
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%cond2 = select i1 %cmp2, half %cond1, half 34.
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ret half %cond2
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}
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define half @fp16_vminnm_NNNule(half %b) {
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; CHECK-LABEL: fp16_vminnm_NNNule:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldr.16 s2, .LCPI15_0
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; CHECK-NEXT: vmov.f16 s0, r0
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; CHECK-NEXT: vminnm.f16 s0, s0, s2
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; CHECK-NEXT: vldr.16 s2, .LCPI15_1
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; CHECK-NEXT: vcmp.f16 s0, s2
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: vselgt.f16 s0, s2, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 1
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI15_0:
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; CHECK-NEXT: .short 0x5040 @ half 34
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; CHECK-NEXT: .LCPI15_1:
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; CHECK-NEXT: .short 0x5300 @ half 56
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entry:
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%cmp1 = fcmp ule half 34., %b
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%cond1 = select i1 %cmp1, half 34., half %b
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%cmp2 = fcmp ule half %cond1, 56.
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%cond2 = select i1 %cmp2, half %cond1, half 56.
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ret half %cond2
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}
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define half @fp16_vminnm_NNNu_rev(half %b) {
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; CHECK-LABEL: fp16_vminnm_NNNu_rev:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldr.16 s2, .LCPI16_0
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; CHECK-NEXT: vmov.f16 s0, r0
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; CHECK-NEXT: vcmp.f16 s0, s2
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: vselge.f16 s0, s2, s0
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; CHECK-NEXT: vldr.16 s2, .LCPI16_1
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; CHECK-NEXT: vminnm.f16 s0, s0, s2
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 1
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI16_0:
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; CHECK-NEXT: .short 0x5300 @ half 56
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; CHECK-NEXT: .LCPI16_1:
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; CHECK-NEXT: .short 0x54e0 @ half 78
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entry:
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%cmp1 = fcmp ugt half 56., %b
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%cond1 = select i1 %cmp1, half %b, half 56.
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%cmp2 = fcmp ugt half %cond1, 78.
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%cond2 = select i1 %cmp2, half 78., half %cond1
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ret half %cond2
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}
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define half @fp16_vmaxnm_NNNo(half %a) {
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; CHECK-LABEL: fp16_vmaxnm_NNNo:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f16 s0, r0
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; CHECK-NEXT: vmov.f16 s2, #1.200000e+01
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; CHECK-NEXT: vmaxnm.f16 s0, s0, s2
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; CHECK-NEXT: vldr.16 s2, .LCPI17_0
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; CHECK-NEXT: vcmp.f16 s2, s0
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: vselgt.f16 s0, s2, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 1
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI17_0:
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; CHECK-NEXT: .short 0x5040 @ half 34
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entry:
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%cmp1 = fcmp ogt half %a, 12.
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%cond1 = select i1 %cmp1, half %a, half 12.
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%cmp2 = fcmp ogt half 34., %cond1
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%cond2 = select i1 %cmp2, half 34., half %cond1
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ret half %cond2
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}
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define half @fp16_vmaxnm_NNNoge(half %a) {
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; CHECK-LABEL: fp16_vmaxnm_NNNoge:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldr.16 s2, .LCPI18_0
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; CHECK-NEXT: vmov.f16 s0, r0
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; CHECK-NEXT: vmaxnm.f16 s0, s0, s2
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; CHECK-NEXT: vldr.16 s2, .LCPI18_1
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; CHECK-NEXT: vcmp.f16 s2, s0
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: vselge.f16 s0, s2, s0
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 1
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI18_0:
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; CHECK-NEXT: .short 0x5040 @ half 34
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; CHECK-NEXT: .LCPI18_1:
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; CHECK-NEXT: .short 0x5300 @ half 56
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entry:
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%cmp1 = fcmp oge half %a, 34.
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%cond1 = select i1 %cmp1, half %a, half 34.
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%cmp2 = fcmp oge half 56., %cond1
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%cond2 = select i1 %cmp2, half 56., half %cond1
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ret half %cond2
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}
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define half @fp16_vmaxnm_NNNo_rev(half %a) {
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; CHECK-LABEL: fp16_vmaxnm_NNNo_rev:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldr.16 s2, .LCPI19_0
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; CHECK-NEXT: vmov.f16 s0, r0
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; CHECK-NEXT: vcmp.f16 s2, s0
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; CHECK-NEXT: vmrs APSR_nzcv, fpscr
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; CHECK-NEXT: vselgt.f16 s0, s2, s0
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; CHECK-NEXT: vldr.16 s2, .LCPI19_1
|
|
; CHECK-NEXT: vmaxnm.f16 s0, s0, s2
|
|
; CHECK-NEXT: vmov r0, s0
|
|
; CHECK-NEXT: bx lr
|
|
; CHECK-NEXT: .p2align 1
|
|
; CHECK-NEXT: @ %bb.1:
|
|
; CHECK-NEXT: .LCPI19_0:
|
|
; CHECK-NEXT: .short 0x5300 @ half 56
|
|
; CHECK-NEXT: .LCPI19_1:
|
|
; CHECK-NEXT: .short 0x54e0 @ half 78
|
|
entry:
|
|
%cmp1 = fcmp olt half %a, 56.
|
|
%cond1 = select i1 %cmp1, half 56., half %a
|
|
%cmp2 = fcmp olt half 78., %cond1
|
|
%cond2 = select i1 %cmp2, half %cond1, half 78.
|
|
ret half %cond2
|
|
}
|
|
|
|
define half @fp16_vmaxnm_NNNole_rev(half %a) {
|
|
; CHECK-LABEL: fp16_vmaxnm_NNNole_rev:
|
|
; CHECK: @ %bb.0: @ %entry
|
|
; CHECK-NEXT: vldr.16 s2, .LCPI20_0
|
|
; CHECK-NEXT: vmov.f16 s0, r0
|
|
; CHECK-NEXT: vcmp.f16 s2, s0
|
|
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
|
|
; CHECK-NEXT: vselge.f16 s0, s2, s0
|
|
; CHECK-NEXT: vldr.16 s2, .LCPI20_1
|
|
; CHECK-NEXT: vmaxnm.f16 s0, s0, s2
|
|
; CHECK-NEXT: vmov r0, s0
|
|
; CHECK-NEXT: bx lr
|
|
; CHECK-NEXT: .p2align 1
|
|
; CHECK-NEXT: @ %bb.1:
|
|
; CHECK-NEXT: .LCPI20_0:
|
|
; CHECK-NEXT: .short 0x54e0 @ half 78
|
|
; CHECK-NEXT: .LCPI20_1:
|
|
; CHECK-NEXT: .short 0x55a0 @ half 90
|
|
entry:
|
|
%cmp1 = fcmp ole half %a, 78.
|
|
%cond1 = select i1 %cmp1, half 78., half %a
|
|
%cmp2 = fcmp ole half 90., %cond1
|
|
%cond2 = select i1 %cmp2, half %cond1, half 90.
|
|
ret half %cond2
|
|
}
|
|
|
|
define half @fp16_vmaxnm_NNNu(half %b) {
|
|
; CHECK-LABEL: fp16_vmaxnm_NNNu:
|
|
; CHECK: @ %bb.0: @ %entry
|
|
; CHECK-NEXT: vmov.f16 s0, r0
|
|
; CHECK-NEXT: vmov.f16 s2, #1.200000e+01
|
|
; CHECK-NEXT: vmaxnm.f16 s0, s0, s2
|
|
; CHECK-NEXT: vldr.16 s2, .LCPI21_0
|
|
; CHECK-NEXT: vcmp.f16 s2, s0
|
|
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
|
|
; CHECK-NEXT: vselge.f16 s0, s2, s0
|
|
; CHECK-NEXT: vmov r0, s0
|
|
; CHECK-NEXT: bx lr
|
|
; CHECK-NEXT: .p2align 1
|
|
; CHECK-NEXT: @ %bb.1:
|
|
; CHECK-NEXT: .LCPI21_0:
|
|
; CHECK-NEXT: .short 0x5040 @ half 34
|
|
entry:
|
|
%cmp1 = fcmp ugt half 12., %b
|
|
%cond1 = select i1 %cmp1, half 12., half %b
|
|
%cmp2 = fcmp ugt half %cond1, 34.
|
|
%cond2 = select i1 %cmp2, half %cond1, half 34.
|
|
ret half %cond2
|
|
}
|
|
|
|
define half @fp16_vmaxnm_NNNuge(half %b) {
|
|
; CHECK-LABEL: fp16_vmaxnm_NNNuge:
|
|
; CHECK: @ %bb.0: @ %entry
|
|
; CHECK-NEXT: vldr.16 s2, .LCPI22_0
|
|
; CHECK-NEXT: vmov.f16 s0, r0
|
|
; CHECK-NEXT: vmaxnm.f16 s0, s0, s2
|
|
; CHECK-NEXT: vldr.16 s2, .LCPI22_1
|
|
; CHECK-NEXT: vcmp.f16 s2, s0
|
|
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
|
|
; CHECK-NEXT: vselgt.f16 s0, s2, s0
|
|
; CHECK-NEXT: vmov r0, s0
|
|
; CHECK-NEXT: bx lr
|
|
; CHECK-NEXT: .p2align 1
|
|
; CHECK-NEXT: @ %bb.1:
|
|
; CHECK-NEXT: .LCPI22_0:
|
|
; CHECK-NEXT: .short 0x5040 @ half 34
|
|
; CHECK-NEXT: .LCPI22_1:
|
|
; CHECK-NEXT: .short 0x5300 @ half 56
|
|
entry:
|
|
%cmp1 = fcmp uge half 34., %b
|
|
%cond1 = select i1 %cmp1, half 34., half %b
|
|
%cmp2 = fcmp uge half %cond1, 56.
|
|
%cond2 = select i1 %cmp2, half %cond1, half 56.
|
|
ret half %cond2
|
|
}
|
|
|
|
define half @fp16_vminmaxnm_neg0(half %a) {
|
|
; CHECK-LABEL: fp16_vminmaxnm_neg0:
|
|
; CHECK: @ %bb.0: @ %entry
|
|
; CHECK-NEXT: vldr.16 s0, .LCPI23_0
|
|
; CHECK-NEXT: vmov.f16 s2, r0
|
|
; CHECK-NEXT: vminnm.f16 s2, s2, s0
|
|
; CHECK-NEXT: vcmp.f16 s0, s2
|
|
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
|
|
; CHECK-NEXT: vselge.f16 s0, s0, s2
|
|
; CHECK-NEXT: vmov r0, s0
|
|
; CHECK-NEXT: bx lr
|
|
; CHECK-NEXT: .p2align 1
|
|
; CHECK-NEXT: @ %bb.1:
|
|
; CHECK-NEXT: .LCPI23_0:
|
|
; CHECK-NEXT: .short 0x8000 @ half -0
|
|
entry:
|
|
%cmp1 = fcmp olt half %a, -0.
|
|
%cond1 = select i1 %cmp1, half %a, half -0.
|
|
%cmp2 = fcmp ugt half %cond1, -0.
|
|
%cond2 = select i1 %cmp2, half %cond1, half -0.
|
|
ret half %cond2
|
|
}
|
|
|
|
define half @fp16_vminmaxnm_e_0(half %a) {
|
|
; CHECK-LABEL: fp16_vminmaxnm_e_0:
|
|
; CHECK: @ %bb.0: @ %entry
|
|
; CHECK-NEXT: vmov.f16 s0, r0
|
|
; CHECK-NEXT: vldr.16 s2, .LCPI24_0
|
|
; CHECK-NEXT: vcmp.f16 s0, #0
|
|
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
|
|
; CHECK-NEXT: vselge.f16 s0, s2, s0
|
|
; CHECK-NEXT: vmaxnm.f16 s0, s0, s2
|
|
; CHECK-NEXT: vmov r0, s0
|
|
; CHECK-NEXT: bx lr
|
|
; CHECK-NEXT: .p2align 1
|
|
; CHECK-NEXT: @ %bb.1:
|
|
; CHECK-NEXT: .LCPI24_0:
|
|
; CHECK-NEXT: .short 0x0000 @ half 0
|
|
entry:
|
|
%cmp1 = fcmp nsz ole half 0., %a
|
|
%cond1 = select i1 %cmp1, half 0., half %a
|
|
%cmp2 = fcmp nsz uge half 0., %cond1
|
|
%cond2 = select i1 %cmp2, half 0., half %cond1
|
|
ret half %cond2
|
|
}
|
|
|
|
define half @fp16_vminmaxnm_e_neg0(half %a) {
|
|
; CHECK-LABEL: fp16_vminmaxnm_e_neg0:
|
|
; CHECK: @ %bb.0: @ %entry
|
|
; CHECK-NEXT: vldr.16 s0, .LCPI25_0
|
|
; CHECK-NEXT: vmov.f16 s2, r0
|
|
; CHECK-NEXT: vminnm.f16 s2, s2, s0
|
|
; CHECK-NEXT: vcmp.f16 s0, s2
|
|
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
|
|
; CHECK-NEXT: vselge.f16 s0, s0, s2
|
|
; CHECK-NEXT: vmov r0, s0
|
|
; CHECK-NEXT: bx lr
|
|
; CHECK-NEXT: .p2align 1
|
|
; CHECK-NEXT: @ %bb.1:
|
|
; CHECK-NEXT: .LCPI25_0:
|
|
; CHECK-NEXT: .short 0x8000 @ half -0
|
|
entry:
|
|
%cmp1 = fcmp nsz ule half -0., %a
|
|
%cond1 = select i1 %cmp1, half -0., half %a
|
|
%cmp2 = fcmp nsz oge half -0., %cond1
|
|
%cond2 = select i1 %cmp2, half -0., half %cond1
|
|
ret half %cond2
|
|
}
|