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f65ec601b0
Fix the ARM backend's analyzeBranch so it doesn't ignore predicated return instructions, and make the MachineVerifier rule more strict. Differential Revision: https://reviews.llvm.org/D40061
58 lines
2.0 KiB
LLVM
58 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm-none-eabi | FileCheck %s
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%struct.anon.1.19.23.27.35.49.55.57.59.61.89.95 = type { i32, i32 }
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@e = external constant [2 x %struct.anon.1.19.23.27.35.49.55.57.59.61.89.95], align 4
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@f = external global i32, align 4
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define arm_aapcscc void @g() {
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; CHECK-LABEL: g:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r11, lr}
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; CHECK-NEXT: push {r11, lr}
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; CHECK-NEXT: ldr r0, .LCPI0_0
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; CHECK-NEXT: mov r2, #0
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; CHECK-NEXT: ldr r1, .LCPI0_1
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: ldr r0, [r0]
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; CHECK-NEXT: ldr r0, [r1, r0, lsl #3]!
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; CHECK-NEXT: moveq r0, #0
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: popne {r11, lr}
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; CHECK-NEXT: movne pc, lr
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; CHECK-NEXT: .LBB0_1: @ %if.then5
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; CHECK-NEXT: ldr r1, [r1, #4]
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; CHECK-NEXT: bl k
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: @ %bb.2:
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; CHECK-NEXT: .LCPI0_0:
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; CHECK-NEXT: .long f
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; CHECK-NEXT: .LCPI0_1:
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; CHECK-NEXT: .long e
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entry:
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%0 = load i32, i32* @f, align 4
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%c = getelementptr inbounds [2 x %struct.anon.1.19.23.27.35.49.55.57.59.61.89.95], [2 x %struct.anon.1.19.23.27.35.49.55.57.59.61.89.95]* @e, i32 0, i32 %0, i32 0
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%1 = load i32, i32* %c, align 4
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%d = getelementptr inbounds [2 x %struct.anon.1.19.23.27.35.49.55.57.59.61.89.95], [2 x %struct.anon.1.19.23.27.35.49.55.57.59.61.89.95]* @e, i32 0, i32 %0, i32 1
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%2 = load i32, i32* %d, align 4
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br i1 undef, label %land.lhs.true, label %if.end
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land.lhs.true: ; preds = %entry
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br label %if.end
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if.end: ; preds = %land.lhs.true, %entry
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%h.0 = phi i32 [ %1, %entry ], [ 0, %land.lhs.true ]
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br i1 undef, label %if.end7, label %if.then5
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if.then5: ; preds = %if.end
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%call6 = call arm_aapcscc i32 bitcast (i32 (...)* @k to i32 (i32, i32)*)(i32 %h.0, i32 %2)
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unreachable
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if.end7: ; preds = %if.end
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ret void
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}
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declare arm_aapcscc i32 @k(...)
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