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https://github.com/RPCS3/llvm-mirror.git
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bbf5be9d55
This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
118 lines
3.5 KiB
YAML
118 lines
3.5 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -o - %s -mtriple=armv7-- -verify-machineinstrs -run-pass=peephole-opt | FileCheck %s
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#
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# Make sure we do not crash on this input.
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# Note that this input could in principle be optimized, but right now we don't
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# have this case implemented so the output should simply be unchanged.
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---
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name: func0
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: func0
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; CHECK: bb.0:
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; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK: Bcc %bb.2, 1 /* CC::ne */, undef $cpsr
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; CHECK: bb.1:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: [[DEF:%[0-9]+]]:dpr = IMPLICIT_DEF
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; CHECK: [[VMOVRRD:%[0-9]+]]:gpr, [[VMOVRRD1:%[0-9]+]]:gpr = VMOVRRD [[DEF]], 14 /* CC::al */, $noreg
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; CHECK: B %bb.3
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; CHECK: bb.2:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: [[DEF1:%[0-9]+]]:spr = IMPLICIT_DEF
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; CHECK: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS [[DEF1]], 14 /* CC::al */, $noreg
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; CHECK: bb.3:
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; CHECK: [[PHI:%[0-9]+]]:gpr = PHI [[VMOVRRD]], %bb.1, [[VMOVRS]], %bb.2
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; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg
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bb.0:
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Bcc %bb.2, 1, undef $cpsr
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bb.1:
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%0:dpr = IMPLICIT_DEF
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%1:gpr, %2:gpr = VMOVRRD %0:dpr, 14, $noreg
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B %bb.3
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bb.2:
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%3:spr = IMPLICIT_DEF
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%4:gpr = VMOVRS %3:spr, 14, $noreg
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bb.3:
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%5:gpr = PHI %1, %bb.1, %4, %bb.2
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%6:spr = VMOVSR %5, 14, $noreg
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...
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---
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name: func1
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: func1
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; CHECK: bb.0:
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; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK: Bcc %bb.2, 1 /* CC::ne */, undef $cpsr
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; CHECK: bb.1:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF
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; CHECK: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS [[DEF]], 14 /* CC::al */, $noreg
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; CHECK: B %bb.3
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; CHECK: bb.2:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: [[DEF1:%[0-9]+]]:spr = IMPLICIT_DEF
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; CHECK: [[VMOVRS1:%[0-9]+]]:gpr = VMOVRS [[DEF1]], 14 /* CC::al */, $noreg
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; CHECK: bb.3:
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; CHECK: [[PHI:%[0-9]+]]:spr = PHI [[DEF]], %bb.1, [[DEF1]], %bb.2
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; CHECK: [[PHI1:%[0-9]+]]:gpr = PHI [[VMOVRS]], %bb.1, [[VMOVRS1]], %bb.2
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; CHECK: [[COPY:%[0-9]+]]:spr = COPY [[PHI]]
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bb.0:
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Bcc %bb.2, 1, undef $cpsr
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bb.1:
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%1:spr = IMPLICIT_DEF
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%0:gpr = VMOVRS %1, 14, $noreg
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B %bb.3
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bb.2:
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%3:spr = IMPLICIT_DEF
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%2:gpr = VMOVRS %3:spr, 14, $noreg
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bb.3:
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%4:gpr = PHI %0, %bb.1, %2, %bb.2
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%5:spr = VMOVSR %4, 14, $noreg
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...
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# The current implementation doesn't perform any transformations if undef
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# operands are involved.
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---
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name: func-undefops
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: func-undefops
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; CHECK: bb.0:
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; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK: Bcc %bb.2, 1 /* CC::ne */, undef $cpsr
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; CHECK: bb.1:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS undef %1:spr, 14 /* CC::al */, $noreg
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; CHECK: B %bb.3
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; CHECK: bb.2:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: [[VMOVRS1:%[0-9]+]]:gpr = VMOVRS undef %3:spr, 14 /* CC::al */, $noreg
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; CHECK: bb.3:
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; CHECK: [[PHI:%[0-9]+]]:gpr = PHI [[VMOVRS]], %bb.1, [[VMOVRS1]], %bb.2
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; CHECK: [[VMOVSR:%[0-9]+]]:spr = VMOVSR [[PHI]], 14 /* CC::al */, $noreg
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bb.0:
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Bcc %bb.2, 1, undef $cpsr
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bb.1:
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%0:gpr = VMOVRS undef %1:spr, 14, $noreg
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B %bb.3
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bb.2:
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%2:gpr = VMOVRS undef %3:spr, 14, $noreg
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bb.3:
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%4:gpr = PHI %0, %bb.1, %2, %bb.2
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%5:spr = VMOVSR %4, 14, $noreg
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...
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