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4afcc6dc52
The v8m.base ISA contains movw, which can operate on an unsigned 16-bit value. Add the pattern that converts an add with a negative value, that could fit into 16-bits when negated, into a sub with that positive value. Differential Revision: https://reviews.llvm.org/D57942 llvm-svn: 353692
86 lines
2.3 KiB
LLVM
86 lines
2.3 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -show-mc-encoding -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
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; RUN: llc -mtriple=armeb-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
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; RUN: llc -mtriple=thumbv6m %s -o - | FileCheck %s --check-prefix=CHECK-V6M
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; RUN: llc -mtriple=thumbv8m.base -show-mc-encoding %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8M
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; RUN: llc -mtriple=thumbv8m.main -show-mc-encoding %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8M
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; 171 = 0x000000ab
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define i64 @f1(i64 %a) {
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; CHECK-LABEL: f1
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; CHECK-LE: subs{{.*}} r0, #171
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; CHECK-LE: sbc r1, r1, #0
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; CHECK-BE: subs r1, r1, #171
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; CHECK-BE: sbc r0, r0, #0
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%tmp = sub i64 %a, 171
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ret i64 %tmp
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}
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; 66846720 = 0x03fc0000
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define i64 @f2(i64 %a) {
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; CHECK-LABEL: f2
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; CHECK-LE: subs{{.*}} r0, r0, #66846720
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; CHECK-LE: sbc r1, r1, #0
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; CHECK-BE: subs r1, r1, #66846720
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; CHECK-BE: sbc r0, r0, #0
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%tmp = sub i64 %a, 66846720
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ret i64 %tmp
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}
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; 734439407618 = 0x000000ab00000002
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define i64 @f3(i64 %a) {
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; CHECK-LABEL: f3
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; CHECK-LE: subs{{.*}} r0, #2
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; CHECK-LE: sbc r1, r1, #171
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; CHECK-BE: subs r1, r1, #2
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; CHECK-BE: sbc r0, r0, #171
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%tmp = sub i64 %a, 734439407618
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ret i64 %tmp
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}
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define i32 @f4(i32 %x) {
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entry:
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; CHECK-LABEL: f4
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; CHECK-LE: rsbs
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; CHECK-BE: rsbs
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%sub = sub i32 1, %x
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%cmp = icmp ugt i32 %sub, 0
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%sel = select i1 %cmp, i32 1, i32 %sub
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ret i32 %sel
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}
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define i32 @f5(i32 %x) {
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entry:
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; CHECK-LABEL: f5:
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; CHECK-LE: movw r1, #65535 @ encoding: [0xff,0x1f,0x0f,0xe3]
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; CHECK-V8M: movw r1, #65535 @ encoding: [0x4f,0xf6,0xff,0x71]
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; CHECK-NOT: movt
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; CHECK-NOT: add
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; CHECK: sub{{.*}} r0, r0, r1
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; CHECK-V6M-LABEL: f5
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; CHECK-V6M: ldr [[NEG:r[0-1]+]], [[CONST:.[A-Z0-9_]+]]
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; CHECK-V6M: add{{.*}} r0, [[NEG]]
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; CHECK-V6M: [[CONST]]
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; CHECK-V6M: .long 4294901761
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%sub = add i32 %x, -65535
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ret i32 %sub
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}
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define i32 @f6(i32 %x) {
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entry:
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; CHECK-LABEL: f6:
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; CHECK-LE: movw r1, #65535 @ encoding: [0xff,0x1f,0x0f,0xe3]
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; CHECK-V8M: movw r1, #65535 @ encoding: [0x4f,0xf6,0xff,0x71]
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; CHECK-NOT: movt
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; CHECK-NOT: sub
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; CHECK: add{{.*}} r0, r1
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; CHECK-V6M-LABEL: f6
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; CHECK-V6M: ldr [[NEG:r[0-1]+]], [[CONST:.[A-Z0-9_]+]]
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; CHECK-V6M: add{{.*}} r0, [[NEG]]
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; CHECK-V6M: [[CONST]]
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; CHECK-V6M: .long 65535
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%sub = sub i32 %x, -65535
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ret i32 %sub
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}
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