Matt Arsenault 9a257a9a17 AMDGPU: Make m0 unallocatable ... m0 may need to be written for spill code, so we don't want general code uses relying on the value stored in it. This introduces a few code quality regressions where copies from m0 are not coalesced into copies of a copy of m0. llvm-svn: 287841		2016-11-24 00:26:40 +00:00
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AArch64	[AArch64LoadStoreOptimizer] Don't treat write to XZR/WZR as a clobber.	2016-11-21 22:51:10 +00:00
AMDGPU	AMDGPU: Make m0 unallocatable	2016-11-24 00:26:40 +00:00
ARM	MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it	2016-08-25 01:27:13 +00:00
Generic	[MIRPrinter] XFAIL test for powerpc	2016-11-18 20:08:05 +00:00
Hexagon	[MIRParser] Parse lane masks for register live-ins	2016-10-12 21:06:45 +00:00
Lanai	MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it	2016-08-25 01:27:13 +00:00
Mips	MIRParser: Use shorter cfi identifiers	2016-07-26 18:20:00 +00:00
NVPTX	llc: Add support for -run-pass none	2016-07-16 02:24:59 +00:00
PowerPC	MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.	2016-08-24 01:32:41 +00:00
X86	[MIRPrinter] Print raw branch probabilities as expected by MIRParser	2016-11-18 19:37:24 +00:00